Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5983012 | Executing programs of a first system on a second system | Richard S. Bianchi, Dennis R. Flynn, Marcia T. Fogelgren, Mary E. Tovell, William E. Woods | 1999-11-09 |
| 5678032 | Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units | William E. Woods, Edward Kumiega | 1997-10-14 |
| 5491790 | Power-on sequencing apparatus for initializing and testing a system processing unit | James W. Keeley, Chester M. Nibby, Jr., Keith L. Petry, Thomas S. Hirsch | 1996-02-13 |
| 5446847 | Programmable system bus priority network | James W. Keeley, George J. Barlow | 1995-08-29 |
| 5375248 | Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories | Steven A. Tague, William E. Woods | 1994-12-20 |
| 5341495 | Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols | Thomas F. Joyce, James W. Keeley, Bruno DiPlacido, Martin Massucci | 1994-08-23 |
| 5341501 | Processor bus access | James W. Keeley, Chester M. Nibby, Jr. | 1994-08-23 |
| 5293384 | Microprocessor bus interface protocol analyzer | James W. Keeley | 1994-03-08 |
| 5291580 | High performance burst read data transfer operation | Raymond D. Bowden, III, Chester M. Nibby, Jr., Jeffrey S. Somers | 1994-03-01 |
| 5280595 | State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections | Steven A. Tague, William E. Woods | 1994-01-18 |
| 5274825 | Microprocessor vectored interrupts | Michael D. Smith | 1993-12-28 |
| 5193181 | Recovery method and apparatus for a pipelined processing unit of a multiprocessor system | George J. Barlow, James W. Keeley, Jian-Kuo Shen, Robert V. Ledoux, Thomas F. Joyce +2 more | 1993-03-09 |
| 5161217 | Buffered address stack register with parallel input registers and overflow protection | Steven A. Tague, Kenneth J. Izbicki, William E. Woods | 1992-11-03 |
| 5142682 | Two-level priority arbiter generating a request to the second level before first-level arbitration is completed | David A. Wallace | 1992-08-25 |
| 5136500 | Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories | Kenneth J. Izbicki, David A. Wallace, William E. Woods | 1992-08-04 |
| 4964037 | Memory addressing arrangement | William E. Woods, David A. Wallace | 1990-10-16 |
| 4935737 | Data selection matrix | Kenneth J. Izbicki, William E. Woods | 1990-06-19 |
| 4903197 | Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank | David A. Wallace | 1990-02-20 |
| 4872110 | Storage of input/output command timeout and acknowledge responses | Michael D. Smith | 1989-10-03 |
| 4837738 | Address boundary detector | William E. Woods, Steven A. Tague | 1989-06-06 |
| 4811266 | Multifunction arithmetic indicator | William E. Woods | 1989-03-07 |
| 4809276 | Memory failure detection apparatus | David A. Wallace | 1989-02-28 |
| 4775929 | Time partitioned bus arrangement | Kenneth J. Izbicki, William E. Woods, Steven A. Taque | 1988-10-04 |
| 4727486 | Hardware demand fetch cycle system interface | Michael D. Smith, Llewelyn S. Dunwell, Robert C. Miller, Theodore R. Staplin, Jr., William E. Woods +1 more | 1988-02-23 |
| 4604685 | Two stage selection based on time of arrival and predetermined priority in a bus priority resolver | Richard P. Brown, G. Lewis Steiner, William E. Woods | 1986-08-05 |