Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5983012 | Executing programs of a first system on a second system | Richard S. Bianchi, Dennis R. Flynn, Marcia T. Fogelgren, Richard A. Lemay, Mary E. Tovell | 1999-11-09 |
| 5678032 | Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units | Richard A. Lemay, Edward Kumiega | 1997-10-14 |
| 5515525 | Emulating the memory functions of a first system on a second system | Marek Grynberg, Dennis R. Flynn, Thomas S. Hirsch, Mary E. Tovell | 1996-05-07 |
| 5442866 | Surveying rule assembly, and methods of constructing and utilizing same | — | 1995-08-22 |
| 5375248 | Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories | Richard A. Lemay, Steven A. Tague | 1994-12-20 |
| 5280595 | State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections | Richard A. Lemay, Steven A. Tague | 1994-01-18 |
| 5243601 | Apparatus and method for detecting a runaway firmware control unit | Steven A. Tague | 1993-09-07 |
| 5161217 | Buffered address stack register with parallel input registers and overflow protection | Richard A. Lemay, Steven A. Tague, Kenneth J. Izbicki | 1992-11-03 |
| 5136500 | Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories | Richard A. Lemay, Kenneth J. Izbicki, David A. Wallace | 1992-08-04 |
| 4964037 | Memory addressing arrangement | Richard A. Lemay, David A. Wallace | 1990-10-16 |
| 4935737 | Data selection matrix | Kenneth J. Izbicki, Richard A. Lemay | 1990-06-19 |
| 4837738 | Address boundary detector | Richard A. Lemay, Steven A. Tague | 1989-06-06 |
| 4811266 | Multifunction arithmetic indicator | Richard A. Lemay | 1989-03-07 |
| 4799181 | BCD arithmetic using binary arithmetic and logical operations | Steven A. Tague | 1989-01-17 |
| 4775929 | Time partitioned bus arrangement | Kenneth J. Izbicki, Richard A. Lemay, Steven A. Taque | 1988-10-04 |
| 4727486 | Hardware demand fetch cycle system interface | Michael D. Smith, Llewelyn S. Dunwell, Richard A. Lemay, Robert C. Miller, Theodore R. Staplin, Jr. +1 more | 1988-02-23 |
| 4604685 | Two stage selection based on time of arrival and predetermined priority in a bus priority resolver | Richard P. Brown, Richard A. Lemay, G. Lewis Steiner | 1986-08-05 |
| 4491908 | Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit | Philip E. Stanley | 1985-01-01 |
| 4472773 | Instruction decoding logic system | Philip E. Stanley, Richard A. Lemay | 1984-09-18 |
| 4467416 | Logic transfer and decoding system | David E. Cushing, Richard A. Lemay, Philip E. Stanley | 1984-08-21 |
| 4467417 | Flexible logic transfer and instruction decoding system | David E. Cushing, Richard A. Lemay, Philip E. Stanley | 1984-08-21 |
| 4460959 | Logic control system including cache memory for CPU-memory transfers | Richard A. Lemay, Philip E. Stanley, David E. Cushing | 1984-07-17 |
| 4455606 | Logic control system for efficient memory to CPU transfers | David E. Cushing, Richard A. Lemay, Philip E. Stanley | 1984-06-19 |
| 4451883 | Bus sourcing and shifter control of a central processing unit | Philip E. Stanley, Richard A. Lemay, David E. Cushing | 1984-05-29 |
| 4432050 | Data processing system write protection mechanism | Robert Harris, Scott W. Ryburn, Henry F. Hartley | 1984-02-14 |