| 5229999 |
Method and apparatus for integrity testing of fault monitoring logic |
Edward Hutchings, Elmer W. Carroll, James F. Bertone |
1993-07-20 |
| 5134706 |
Bus interface interrupt apparatus |
Ralph M. Lombardo, Jr., Forrest M. Phillips |
1992-07-28 |
| 5003204 |
Edge triggered D-type flip-flop scan latch cell with recirculation capability |
John A. DeFalco |
1991-03-26 |
| 4980819 |
Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system |
Richard P. Kelly, Robert V. Ledoux, Jian-Kuo Shen |
1990-12-25 |
| 4933909 |
Dual read/write register file memory |
Romeo Kharileh, Jian-Kuo Shen, Ming T. Miu |
1990-06-12 |
| 4467417 |
Flexible logic transfer and instruction decoding system |
William E. Woods, Richard A. Lemay, Philip E. Stanley |
1984-08-21 |
| 4467416 |
Logic transfer and decoding system |
Richard A. Lemay, Philip E. Stanley, William E. Woods |
1984-08-21 |
| 4460959 |
Logic control system including cache memory for CPU-memory transfers |
Richard A. Lemay, Philip E. Stanley, William E. Woods |
1984-07-17 |
| 4455606 |
Logic control system for efficient memory to CPU transfers |
Richard A. Lemay, Philip E. Stanley, William E. Woods |
1984-06-19 |
| 4451883 |
Bus sourcing and shifter control of a central processing unit |
Philip E. Stanley, William E. Woods, Richard A. Lemay |
1984-05-29 |
| 4438493 |
Multiwork memory data storage and addressing technique and apparatus |
Philip E. Stanley |
1984-03-20 |
| 4360869 |
Control store organization for a data processing system |
Philip E. Stanley, Donald R. Taylor |
1982-11-23 |
| 4349874 |
Buffer system for supply procedure words to a central processor unit |
William E. Woods, Philip E. Stanley, Richard A. Lemay |
1982-09-14 |
| 4348723 |
Control store test selection logic for a data processing system |
William E. Woods, Philip E. Stanley |
1982-09-07 |
| 4348724 |
Address pairing apparatus for a control store of a data processing system |
Philip E. Stanley |
1982-09-07 |
| 4323967 |
Local bus interface for controlling information transfers between units in a central subsystem |
Arthur Peters, Virendra S. Negi, Richard P. Brown, Thomas F. Joyce |
1982-04-06 |
| 4295202 |
Hexadecimal digit shifter output control by a programmable read only memory |
THOMAS J JOYCE |
1981-10-13 |