Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5123097 | Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy | Thomas F. Joyce, Richard P. Kelly | 1992-06-16 |
| 5073855 | Resource conflict detection method and apparatus included in a pipelined processing unit | Deborah K. Staplin, Jian-Kuo Shen | 1991-12-17 |
| 5051894 | Apparatus and method for address translation of non-aligned double word virtual addresses | Forrest M. Phillips, Thomas F. Joyce | 1991-09-24 |
| 4933909 | Dual read/write register file memory | David E. Cushing, Romeo Kharileh, Jian-Kuo Shen | 1990-06-12 |
| 4785398 | Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page | Thomas F. Joyce, Jian-Kuo Shen, Forrest M. Phillips | 1988-11-15 |
| 4783735 | Least recently used replacement level generating apparatus | Thomas F. Joyce, Jian-Kuo Shen, Forrest M. Phillips | 1988-11-08 |
| 4608659 | Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands | John J. Bradley, Theodore R. Staplin, Jr., Thomas C. O'Brien, George M. O'Har, Melinda A. Widen +1 more | 1986-08-26 |
| 4495571 | Data processing system having synchronous bus wait/retry cycle | Theodore R. Staplin, Jr., John J. Bradley, Richard King, Robert C. Miller, Jian-Kuo Shen | 1985-01-22 |
| 4488227 | Program counter stacking method and apparatus for nested subroutines and interrupts | John J. Bradley | 1984-12-11 |
| 4484271 | Microprogrammed system having hardware interrupt apparatus | John J. Bradley, Jian-Kuo Shen | 1984-11-20 |
| 4459665 | Data processing system having centralized bus priority resolution | John J. Bradley, Jian-Kuo Shen | 1984-07-10 |
| 4387423 | Microprogrammed system having single microstep apparatus | Richard King, John J. Bradley | 1983-06-07 |
| 4383295 | Data processing system having data entry backspace character apparatus | Robert C. Miller, John J. Bradley, Boyd E. Darden, Jian-Kuo Shen, Theodore R. Staplin, Jr. | 1983-05-10 |
| 4340933 | Data processing system having centralized nonexistent memory address detection | John J. Bradley, William Panepinto, Jr., Jian-Kuo Shen | 1982-07-20 |
| 4321665 | Data processing system having centralized data alignment for I/O controllers | Jian-Kuo Shen, John J. Bradley, Richard King, Robert C. Miller, Theodore R. Staplin, Jr. | 1982-03-23 |
| 4317169 | Data processing system having centralized memory refresh | William Panepinto, Jr., Chester M. Nibby, Jr., Jian-Kuo Shen | 1982-02-23 |
| 4300193 | Data processing system having data multiplex control apparatus | John J. Bradley, Robert C. Miller, Jian-Kuo Shen, Theodore R. Staplin, Jr. | 1981-11-10 |
| 4300194 | Data processing system having multiple common buses | John J. Bradley, Jian-Kuo Shen | 1981-11-10 |
| 4293908 | Data processing system having direct memory access bus cycle | John J. Bradley, Thomas O. Holtey, Robert C. Miller, Jian-Kuo Shen, Theodore R. Staplin, Jr. | 1981-10-06 |
| 4292668 | Data processing system having data multiplex control bus cycle | Robert C. Miller, John J. Bradley, Richard King, Jian-Kuo Shen, Theodore R. Staplin, Jr. | 1981-09-29 |
| 4218739 | Data processing interrupt apparatus having selective suppression control | Virendra S. Negi | 1980-08-19 |