| 5379378 |
Data processing system having a bus command generated by one subsystem on behalf of another subsystem |
Richard C. Zelley, Elmer W. Carroll, George J. Barlow, Chester M. Nibby, Jr., James W. Keeley |
1995-01-03 |
$4,299,000 |
| 5274797 |
Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing |
George J. Barlow, Elmer W. Carroll, James W. Keeley, Wallace A. Martland, Victor M. Morganti +1 more |
1993-12-28 |
$4,276,000 |
| 5226153 |
Bus monitor with time stamp means for independently capturing and correlating events |
Douglas J. DeAngelis, Henry W. J. Maddox, Donald J. Rathbun |
1993-07-06 |
$4,576,000 |
| 5210862 |
Bus monitor with selective capture of independently occuring events from multiple sources |
Douglas J. DeAngelis, Henry W. J. Maddox, Donald J. Rathbun, William L. Saltmarsh |
1993-05-11 |
$6,334,000 |
| 5206948 |
Bus monitor with means for selectively capturing trigger conditions |
Douglas J. De Angelis, Henry W. J. Maddox, Donald J. Rathbun, William L. Saltmarsh |
1993-04-27 |
$9,436,000 |
| 5142673 |
Bus monitor with dual port memory for storing selectable trigger patterns |
Douglas J. De Angelis, Henry W. J. Maddox, Donald J. Rathbun, William L. Saltmarsh |
1992-08-25 |
$5,757,000 |
| 4827400 |
Segment descriptor present bit recycle and detect logic for a memory management unit |
Llewelyn S. Dunwell, Richard P. Brown, John L. Curley |
1989-05-02 |
|
| 4761855 |
Device and method for filleting fish |
— |
1988-08-09 |
|
| 4639860 |
Wrap-around logic for interprocessor communications |
— |
1987-01-27 |
$4,518,000 |
| 4494190 |
FIFO buffer to cache memory |
— |
1985-01-15 |
$3,140,000 |
| 4445172 |
Data steering logic for the output of a cache memory having an odd/even bank structure |
Philip E. Stanley |
1984-04-24 |
$3,009,000 |
| 4424561 |
Odd/even bank structure for a cache memory |
Philip E. Stanley, Richard P. Brown |
1984-01-03 |
$6,075,000 |
| 4392201 |
Diagnostic subsystem for a cache memory |
Richard P. Brown, George J. Barlow |
1983-07-05 |
$5,419,000 |
| 4363095 |
Hit/miss logic for a cache memory |
William E. Woods |
1982-12-07 |
$2,684,000 |
| 4323967 |
Local bus interface for controlling information transfers between units in a central subsystem |
Virendra S. Negi, David E. Cushing, Richard P. Brown, Thomas F. Joyce |
1982-04-06 |
$3,123,000 |
| 4322846 |
Self-evaluation system for determining the operational integrity of a data processing system |
Elmer W. Carroll, Virendra S. Negi |
1982-03-30 |
$1,490,000 |
| 4309753 |
Apparatus and method for next address generation in a data processing system |
Virendra S. Negi |
1982-01-05 |
$2,124,000 |
| 4272828 |
Arithmetic logic apparatus for a data processing system |
Virendra S. Negi |
1981-06-09 |
$10,261,000 |
| 4271484 |
Condition code accumulator apparatus for a data processing system |
Virendra S. Negi |
1981-06-02 |
$2,319,000 |
| 4258420 |
Control file apparatus for a data processing system |
Virendra S. Negi |
1981-03-24 |
$4,869,000 |
| 4245328 |
Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit |
Virendra S. Negi |
1981-01-13 |
$1,995,000 |
| 4224668 |
Control store address generation logic for a data processing system |
Virendra S. Negi |
1980-09-23 |
$2,342,000 |
