Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8866830 | Memory controller interface for micro-tiled memory access | James Akiyama, Douglas Gabel | 2014-10-21 |
| 8310854 | Identifying and accessing individual memory devices in a memory channel | James Akiyama, Kuljit S. Bains, Douglas Gabel | 2012-11-13 |
| 8253751 | Memory controller interface for micro-tiled memory access | James Akiyama, Douglas Gabel | 2012-08-28 |
| 8200883 | Micro-tile memory interfaces | James Akiyama, Douglas Gabel | 2012-06-12 |
| 8064237 | Identifying and accessing individual memory devices in a memory channel | James Akiyama, Kuljit S. Bains, Douglas Gabel | 2011-11-22 |
| 8032688 | Micro-tile memory interfaces | James Akiyama, Douglas Gabel | 2011-10-04 |
| 7872892 | Identifying and accessing individual memory devices in a memory channel | James Akiyama, Kuljit S. Bains, Douglas Gabel | 2011-01-18 |
| RE40921 | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system | William S. Wu, Stephen S. Pawlowski, Muthurajan Jayakumar | 2009-09-22 |
| RE38388 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Stephen S. Pawlowski, Michael W. Rhodehamel | 2004-01-13 |
| 6633947 | Memory expansion channel for propagation of control and request packets | Thomas J. Holman | 2003-10-14 |
| 6598103 | Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system | William S. Wu, Dilip K. Sampath, Bindi A. Prasad | 2003-07-22 |
| 6587912 | Method and apparatus for implementing multiple memory buses on a memory module | Michael W. Leddige, Bryce Horine, Randy M. Bonella | 2003-07-01 |
| 6519735 | Method and apparatus for detecting errors in data output from memory and a device failure in the memory | Thomas J. Holman | 2003-02-11 |
| 6477614 | Method for implementing multiple memory buses on a memory module | Michael W. Leddige, Bryce Horine, Randy M. Bonella | 2002-11-05 |
| 6442632 | System resource arbitration mechanism for a host bridge | George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, James M. Dodd | 2002-08-27 |
| 6412060 | Method and apparatus for supporting multiple overlapping address spaces on a shared bus | Stephen S. Pawlowski | 2002-06-25 |
| 6405271 | Data flow control mechanism for a bus supporting two-and three-agent transactions | Nitin V. Sarangdhar, Stephen S. Pawlowski, Gurbir Singh | 2002-06-11 |
| 6397291 | Method and apparatus for retrieving data from a data storage device | Randy M. Bonella, Konrad K. Lai | 2002-05-28 |
| 6336159 | Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system | William S. Wu, Dilip K. Sampath, Bindi A. Prasad | 2002-01-01 |
| 6253302 | Method and apparatus for supporting multiple overlapping address spaces on a shared bus | Stephen S. Pawlowski | 2001-06-26 |
| 6247136 | Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment | Harry Muljono, Thomas J. Mozdzen | 2001-06-12 |
| 6226757 | Apparatus and method for bus timing compensation | Frederick A. Ware, Richard M. Barth, Donald C. Stark, Craig E. Hampel, Ely Tsern +3 more | 2001-05-01 |
| 6212589 | System resource arbitration mechanism for a host bridge | George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, James M. Dodd | 2001-04-03 |
| 6209072 | Source synchronous interface between master and slave using a deskew latch | Bindi A. Prasad, Manoji Khare, Dilip K. Sampath | 2001-03-27 |
| 6202125 | Processor-cache protocol using simple commands to implement a range of cache configurations | Dan Patterson, Bindi A. Prasad, Gurbir Singh, Steve Hunt, Phil Gi Lee | 2001-03-13 |