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Peter D. MacWilliams — 61 Patents

Intel: 61 patents #470 of 30,777Top 2%
RARambus: 2 patents #324 of 549Top 60%
Beaverton, OR: #72 of 3,140 inventorsTop 3%
Oregon: #510 of 28,073 inventorsTop 2%
Overall (All Time): #37,626 of 4,157,543Top 1%
61 Patents All Time
Peter D. MacWilliams has been granted 61 US patents while listed as an inventor at Intel. The first was granted in 1988 and the most recent in October 2014. Peter D. MacWilliams ranks #37,626 of 4,157,543 US inventors in our database (top 0.91%). Patent records list Peter D. MacWilliams in Beaverton, OR, US.

Issued Patents All Time

Showing 1–25 of 61 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8866830 Memory controller interface for micro-tiled memory access James Akiyama, Douglas Gabel 2014-10-21 $23,195,000
8310854 Identifying and accessing individual memory devices in a memory channel James Akiyama, Kuljit S. Bains, Douglas Gabel 2012-11-13 $15,347,000
8253751 Memory controller interface for micro-tiled memory access James Akiyama, Douglas Gabel 2012-08-28 $14,908,000
8200883 Micro-tile memory interfaces James Akiyama, Douglas Gabel 2012-06-12 $26,197,000
8064237 Identifying and accessing individual memory devices in a memory channel James Akiyama, Kuljit S. Bains, Douglas Gabel 2011-11-22 $16,463,000
8032688 Micro-tile memory interfaces James Akiyama, Douglas Gabel 2011-10-04 $13,316,000
7872892 Identifying and accessing individual memory devices in a memory channel James Akiyama, Kuljit S. Bains, Douglas Gabel 2011-01-18 $38,657,000
RE40921 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system William S. Wu, Stephen S. Pawlowski, Muthurajan Jayakumar 2009-09-22
RE38388 Method and apparatus for performing deferred transactions Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Stephen S. Pawlowski, Michael W. Rhodehamel 2004-01-13
6633947 Memory expansion channel for propagation of control and request packets Thomas J. Holman 2003-10-14 $51,971,000
6598103 Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system William S. Wu, Dilip K. Sampath, Bindi A. Prasad 2003-07-22 $27,595,000
6587912 Method and apparatus for implementing multiple memory buses on a memory module Michael W. Leddige, Bryce Horine, Randy M. Bonella 2003-07-01 $52,453,000
6519735 Method and apparatus for detecting errors in data output from memory and a device failure in the memory Thomas J. Holman 2003-02-11 $38,289,000
6477614 Method for implementing multiple memory buses on a memory module Michael W. Leddige, Bryce Horine, Randy M. Bonella 2002-11-05 $89,631,000
6442632 System resource arbitration mechanism for a host bridge George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, James M. Dodd 2002-08-27 $48,184,000
6412060 Method and apparatus for supporting multiple overlapping address spaces on a shared bus Stephen S. Pawlowski 2002-06-25 $55,737,000
6405271 Data flow control mechanism for a bus supporting two-and three-agent transactions Nitin V. Sarangdhar, Stephen S. Pawlowski, Gurbir Singh 2002-06-11 $104,024,000
6397291 Method and apparatus for retrieving data from a data storage device Randy M. Bonella, Konrad K. Lai 2002-05-28 $93,259,000
6336159 Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system William S. Wu, Dilip K. Sampath, Bindi A. Prasad 2002-01-01
6253302 Method and apparatus for supporting multiple overlapping address spaces on a shared bus Stephen S. Pawlowski 2001-06-26 $197,004,000
6247136 Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment Harry Muljono, Thomas J. Mozdzen 2001-06-12 $172,053,000
6226757 Apparatus and method for bus timing compensation Frederick A. Ware, Richard M. Barth, Donald C. Stark, Craig E. Hampel, Ely Tsern +3 more 2001-05-01
6212589 System resource arbitration mechanism for a host bridge George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, James M. Dodd 2001-04-03 $111,247,000
6209072 Source synchronous interface between master and slave using a deskew latch Bindi A. Prasad, Manoji Khare, Dilip K. Sampath 2001-03-27 $117,605,000
6202125 Processor-cache protocol using simple commands to implement a range of cache configurations Dan Patterson, Bindi A. Prasad, Gurbir Singh, Steve Hunt, Phil Gi Lee 2001-03-13 $189,401,000