Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5513331 | Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset | Stephen S. Pawlowski | 1996-04-30 |
| 5488639 | Parallel multistage synchronization method and apparatus | Dror Avni, Avi Liebermensch, Anan Baransy, Robert L. Farrell | 1996-01-30 |
| 5471637 | Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer | Stephen S. Pawlowski, Jerzy Kolinski | 1995-11-28 |
| 5455957 | Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol | Stephen S. Pawlowski | 1995-10-03 |
| 5421734 | Method and apparatus for evolving bus from five volt to three point three volt operation | — | 1995-06-06 |
| 5355467 | Second level cache controller unit and system | Robert L. Farrell, Adalberto Golbert, Itzik Silas | 1994-10-11 |
| 5301299 | Optimized write protocol for memory accesses utilizing row and column strobes | Stephen S. Pawlowski | 1994-04-05 |
| 5293603 | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path | Clair Webb, Robert L. Farrell | 1994-03-08 |
| 5239638 | Two strobed memory access | Stephen S. Pawlowski | 1993-08-24 |
| 5228134 | Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus | Clair Webb, Robert L. Farrell | 1993-07-13 |
| 4785396 | Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit | Sean T. Murphy, Narjala Bhasker, Stephen J. Packer | 1988-11-15 |