Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6192459 | Method and apparatus for retrieving data from a data storage device | Randy M. Bonella, Konrad K. Lai | 2001-02-20 |
| 6128748 | Independent timing compensation of write data path and read data path on a common data bus | Duane G. Quiet | 2000-10-03 |
| 6112016 | Method and apparatus for sharing a signal line between agents | Norman J. Rasmussen, Nicholas D. Wade, William S. Wu | 2000-08-29 |
| 6075730 | High performance cost optimized memory with delayed memory writes | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis +5 more | 2000-06-13 |
| 6012118 | Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus | Muthurajan Jayakumar, Sunny C. Huang, William S. Wu, Stephen S. Pawlowski, Bindi A. Prasad | 2000-01-04 |
| 5996042 | Scalable, high bandwidth multicard memory system utilizing a single memory controller | Stephen S. Pawlowski | 1999-11-30 |
| 5961621 | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system | William S. Wu, Stephen S. Pawlowski, Muthurajan Jayakumar | 1999-10-05 |
| 5948094 | Method and apparatus for executing multiple transactions within a single arbitration cycle | Gary Solomon, Norman J. Rasmussen | 1999-09-07 |
| 5937171 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh | 1999-08-10 |
| 5923857 | Method and apparatus for ordering writeback data transfers on a bus | Stephen S. Pawlowski, Nitin V. Sarangdhar, Gurbir Singh | 1999-07-13 |
| 5919254 | Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system | Stephen S. Pawlowski, William S. Wu, Len Schultz | 1999-07-06 |
| 5911053 | Method and apparatus for changing data transfer widths in a computer system | Stephen S. Pawlowski, Gurbir Singh | 1999-06-08 |
| 5906001 | Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines | William S. Wu, Stephen S. Pawlowski | 1999-05-18 |
| 5905876 | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system | Stephen S. Pawlowski, D. Michael Bell | 1999-05-18 |
| 5903916 | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation | Stephen S. Pawlowski, Sridhar Lakshmanamurthy | 1999-05-11 |
| 5822767 | Method and apparartus for sharing a signal line between agents | Norman J. Rasmussen, Nicholas D. Wade, William S. Wu | 1998-10-13 |
| 5818794 | Internally controlled signal system for controlling the operation of a device | Randy M. Bonella | 1998-10-06 |
| 5796977 | Highly pipelined bus architecture | Nitin V. Sarangdhar, Gurbir Singh, Konrad K. Lai, Stephen S. Pawlowski, Michael W. Rhodehamel | 1998-08-18 |
| 5784579 | Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth | Stephen S. Pawlowski, Nitin V. Sarangdhar, Michael W. Rhodehamel, Matthew A. Fisch | 1998-07-21 |
| 5651137 | Scalable cache attributes for an input/output bus | Norman J. Rasmussen, Nicholas D. Wade, William S. Wu | 1997-07-22 |
| 5625779 | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | Gary Solomon, George R. Hayek, Nicholas D. Wade, Abid Asghar | 1997-04-29 |
| 5615343 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Stephen S. Pawlowski, Michael W. Rhodehamel | 1997-03-25 |
| 5572703 | Method and apparatus for snoop stretching using signals that convey snoop results | Nitin V. Sarangdhar, Matthew A. Fisch, Amit Merchant | 1996-11-05 |
| 5555423 | Multi-mode microprocessor having a pin for resetting its register without purging its cache | Edward T. Grochowski | 1996-09-10 |
| 5537640 | Asynchronous modular bus architecture with cache consistency | Stephen S. Pawlowski, David Cowan, Howard S. David | 1996-07-16 |