| 11307902 |
Preventing deployment failures of information technology workloads |
Hariharan N. Venkitachalam, Harish Bhatt, Prashant Pareek |
2022-04-19 |
$3,801,000 |
| 9178770 |
Auto incorporation of new components into a hierarchical network |
Venkatesh Patil, Praveen Vyas |
2015-11-03 |
$3,716,000 |
| 9178939 |
Auto incorporation of new components into a hierarchical network |
Venkatesh Patil, Praveen Vyas |
2015-11-03 |
$3,716,000 |
| 8898434 |
Optimizing system throughput by automatically altering thread co-execution based on operating system directives |
Dipankar Sarma, Vaidyanathan Srinivasan |
2014-11-25 |
|
| 8898435 |
Optimizing system throughput by automatically altering thread co-execution based on operating system directives |
Dipankar Sarma, Vaidyanathan Srinivasan |
2014-11-25 |
|
| 7366879 |
Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses |
Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu |
2008-04-29 |
$13,885,000 |
| 7353370 |
Method and apparatus for processing an event occurrence within a multithreaded processor |
Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur |
2008-04-01 |
$16,890,000 |
| 7219349 |
Multi-threading techniques for a processor utilizing a replay queue |
Darrell D. Boggs, David J. Sager |
2007-05-15 |
$17,522,000 |
| 7200737 |
Processor with a replay system that includes a replay queue for improved throughput |
Darrell D. Boggs, David J. Sager |
2007-04-03 |
$17,128,000 |
| 7089409 |
Interface to a memory system for a processor having a replay system |
Darrell D. Boggs, David J. Sager |
2006-08-08 |
$12,359,000 |
| 7039794 |
Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor |
Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur |
2006-05-02 |
$12,289,000 |
| 6889319 |
Method and apparatus for entering and exiting multiple threads within a multithreaded processor |
Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu |
2005-05-03 |
$20,343,000 |
| 6792446 |
Storing of instructions relating to a stalled thread |
Darrell Buggs, David J. Sager |
2004-09-14 |
$15,917,000 |
| 6785803 |
Processor including replay queue to break livelocks |
David J. Sager, James D. Allen, IV |
2004-08-31 |
$18,815,000 |
| 6772322 |
Method and apparatus to monitor the performance of a processor |
Selim Bilgin, Brinkley Sprunt |
2004-08-03 |
$15,005,000 |
| 6665792 |
Interface to a memory system for a processor having a replay system |
Darrell D. Boggs, David J. Sager |
2003-12-16 |
$48,093,000 |
| 6496925 |
Method and apparatus for processing an event occurrence within a multithreaded processor |
Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur |
2002-12-17 |
$45,119,000 |
| 6385715 |
Multi-threading for a processor utilizing a replay queue |
Darrell D. Boggs, David J. Sager |
2002-05-07 |
$68,605,000 |
| 6334182 |
Scheduling operations using a dependency matrix |
David J. Sager |
2001-12-25 |
|
| 6212626 |
Computer processor having a checker |
David J. Sager |
2001-04-03 |
$111,247,000 |
| 6163838 |
Computer processor with a replay system |
David J. Sager, Darrell D. Boggs |
2000-12-19 |
$157,542,000 |
| 6094717 |
Computer processor with a replay system having a plurality of checkers |
David J. Sager, Darrell D. Boggs, Michael D. Upton |
2000-07-25 |
$293,482,000 |
| 5909699 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency |
Nitin V. Sarangdhar, Michael W. Rhodehamel, Matthew A. Fisch, James M. Brayton |
1999-06-01 |
$142,810,000 |
| 5893151 |
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests |
— |
1999-04-06 |
$71,710,000 |
| 5890200 |
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests |
— |
1999-03-30 |
$45,277,000 |
