AM

Amit Merchant

IN Intel: 33 patents #1,094 of 30,777Top 4%
IBM: 2 patents #32,839 of 70,183Top 50%
LP Lenovo (Singapore) Pte.: 2 patents #296 of 1,012Top 30%
KY Kyndryl: 1 patents #287 of 874Top 35%
Overall (All Time): #86,083 of 4,157,543Top 3%
38
Patents All Time

Issued Patents All Time

Showing 25 most recent of 38 patents

Patent #TitleCo-InventorsDate
11307902 Preventing deployment failures of information technology workloads Hariharan N. Venkitachalam, Harish Bhatt, Prashant Pareek 2022-04-19
9178770 Auto incorporation of new components into a hierarchical network Venkatesh Patil, Praveen Vyas 2015-11-03
9178939 Auto incorporation of new components into a hierarchical network Venkatesh Patil, Praveen Vyas 2015-11-03
8898434 Optimizing system throughput by automatically altering thread co-execution based on operating system directives Dipankar Sarma, Vaidyanathan Srinivasan 2014-11-25
8898435 Optimizing system throughput by automatically altering thread co-execution based on operating system directives Dipankar Sarma, Vaidyanathan Srinivasan 2014-11-25
7366879 Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu 2008-04-29
7353370 Method and apparatus for processing an event occurrence within a multithreaded processor Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur 2008-04-01
7219349 Multi-threading techniques for a processor utilizing a replay queue Darrell D. Boggs, David J. Sager 2007-05-15
7200737 Processor with a replay system that includes a replay queue for improved throughput Darrell D. Boggs, David J. Sager 2007-04-03
7089409 Interface to a memory system for a processor having a replay system Darrell D. Boggs, David J. Sager 2006-08-08
7039794 Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur 2006-05-02
6889319 Method and apparatus for entering and exiting multiple threads within a multithreaded processor Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu 2005-05-03
6792446 Storing of instructions relating to a stalled thread Darrell Buggs, David J. Sager 2004-09-14
6785803 Processor including replay queue to break livelocks David J. Sager, James D. Allen, IV 2004-08-31
6772322 Method and apparatus to monitor the performance of a processor Selim Bilgin, Brinkley Sprunt 2004-08-03
6665792 Interface to a memory system for a processor having a replay system Darrell D. Boggs, David J. Sager 2003-12-16
6496925 Method and apparatus for processing an event occurrence within a multithreaded processor Dion Rodgers, Darrell D. Boggs, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur 2002-12-17
6385715 Multi-threading for a processor utilizing a replay queue Darrell D. Boggs, David J. Sager 2002-05-07
6334182 Scheduling operations using a dependency matrix David J. Sager 2001-12-25
6212626 Computer processor having a checker David J. Sager 2001-04-03
6163838 Computer processor with a replay system David J. Sager, Darrell D. Boggs 2000-12-19
6094717 Computer processor with a replay system having a plurality of checkers David J. Sager, Darrell D. Boggs, Michael D. Upton 2000-07-25
5909699 Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency Nitin V. Sarangdhar, Michael W. Rhodehamel, Matthew A. Fisch, James M. Brayton 1999-06-01
5893151 Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests 1999-04-06
5890200 Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests 1999-03-30