Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6668309 | Snoop blocking for cache coherency | Derek T. Bachand, Paul Breuder | 2003-12-23 |
| 6578116 | Snoop blocking for cache coherency | Derek T. Bachand, Paul Breuder | 2003-06-10 |
| 6460119 | Snoop blocking for cache coherency | Derek T. Bachand, Paul Breuder | 2002-10-01 |
| 6268749 | Core clock correction in a 2/n mode clocking scheme | Chakrapani Pathikonda, Javed S. Barkatullah | 2001-07-31 |
| 6216208 | Prefetch queue responsive to read request sequences | Robert Greiner, David L. Hill, Chinna Prudvi, Derek T. Bachand | 2001-04-10 |
| 6209068 | Read line buffer and signaling protocol for processor | David L. Hill, Chinna Prudvi, Derek T. Bachand | 2001-03-27 |
| 6208180 | Core clock correction in a 2/N mode clocking scheme | Chakrapani Pathikonda, Javed S. Barkatullah | 2001-03-27 |
| 6114887 | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme | Chakrapani Pathikonda, Michael W. Rhodehamel | 2000-09-05 |
| 6078981 | Transaction stall technique to prevent livelock in multiple-processor systems | David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder | 2000-06-20 |
| 6009477 | Bus agent providing dynamic pipeline depth control | Nitin V. Sarangdhar, Michael W. Rhodehamel | 1999-12-28 |
| 6006299 | Apparatus and method for caching lock conditions in a multi-processor system | Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Mandar Joshi, Nitin V. Sarangdhar | 1999-12-21 |
| 5948088 | Bus system providing dynamic control of pipeline depth for a multi-agent computer | Nitin V. Sarangdhar, Michael W. Rhodehamel | 1999-09-07 |
| 5909699 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Nitin V. Sarangdhar, Michael W. Rhodehamel, Amit Merchant, James M. Brayton | 1999-06-01 |
| 5901297 | Initialization mechanism for symmetric arbitration agents | Michael W. Rhodehamel, Nitin V. Sarangdhar | 1999-05-04 |
| 5896513 | Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols | James E. Jacobson, Jr., Michael W. Rhodehamel | 1999-04-20 |
| 5845107 | Signaling protocol conversion between a processor and a high-performance system bus | James E. Jacobson, Jr., Michael W. Rhodehamel | 1998-12-01 |
| 5834956 | Core clock correction in a 2/N mode clocking scheme | Chakrapani Pathikonda, Javed S. Barkatullah | 1998-11-10 |
| 5826067 | Method and apparatus for preventing logic glitches in a 2/n clocking scheme | Chakrapani Pathikonda | 1998-10-20 |
| 5802132 | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme | Chakrapani Pathikonda, Michael W. Rhodehamel | 1998-09-01 |
| 5797026 | Method and apparatus for self-snooping a bus during a boundary transaction | Michael W. Rhodehamel, Nitin V. Sarangdhar, Amit Merchant, James M. Brayton | 1998-08-18 |
| 5784579 | Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth | Stephen S. Pawlowski, Nitin V. Sarangdhar, Michael W. Rhodehamel, Peter D. MacWilliams | 1998-07-21 |
| 5778441 | Method and apparatus for accessing split lock variables in a computer system | Michael W. Rhodehamel, Nitin V. Sarangdhar | 1998-07-07 |
| 5774700 | Method and apparatus for determining the timing of snoop windows in a pipelined bus | Nitin V. Sarangdhar | 1998-06-30 |
| 5764934 | Processor subsystem for use with a universal computer architecture | James E. Jacobson, Jr., Michael W. Rhodehamel | 1998-06-09 |
| 5761449 | Bus system providing dynamic control of pipeline depth for a multi-agent computer | Nitin V. Sarangdhar, Michael W. Rhodehamel | 1998-06-02 |