Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Chinna Prudvi — 17 Patents

Intel: 17 patents #2,442 of 30,777Top 8%
Portland, OR: #1,103 of 9,213 inventorsTop 15%
Oregon: #2,576 of 28,073 inventorsTop 10%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Chinna Prudvi has been granted 17 US patents while listed as an inventor at Intel. The first was granted in 2000 and the most recent in February 2019. Chinna Prudvi ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Chinna Prudvi in Portland, OR, US.

Patents per Year

Patents granted per year, 2000 to 2019Bar chart with a peak of 5 patents in 2002.peak 52000: 1 patents20002001: 3 patents20012002: 5 patents20022003: 3 patents20032004: 1 patents20042006: 1 patents20062009: 1 patents20092012: 1 patents20122019: 1 patents2019

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10198333 Test, validation, and debug architecture Mark B. Trobough, Keshavan Tiruvallur, Christian Iovin, David W. Grawrock, Jay Nejedlo +37 more 2019-02-05 $24,217,000
8122194 Transaction manager and cache for processing agent Derek T. Bachand 2012-02-21 $21,312,000
7555603 Transaction manager and cache for processing agent Derek T. Bachand 2009-06-30 $20,585,000
7143242 Dynamic priority external transaction system David L. Hill, Derek T. Bachand, Deborah T. Marr 2006-11-28 $16,743,000
6735675 Method and apparatus for altering data length to zero to maintain cache coherency Paul Breuder, Derek T. Bachand, David L. Hill 2004-05-11 $33,328,000
6654837 Dynamic priority external transaction system David L. Hill, Derek T. Bachand, Deborah T. Marr 2003-11-25 $50,228,000
6578114 Method and apparatus for altering data length to zero to maintain cache coherency Paul Breuder, Derek T. Bachand, David L. Hill 2003-06-10 $73,878,000
6557081 Prefetch queue David L. Hill 2003-04-29 $39,757,000
6484239 Prefetch queue David L. Hill 2002-11-19 $76,016,000
6434677 Method and apparatus for altering data length to zero to maintain cache coherency Paul Breuder, Derek T. Bachand, David L. Hill 2002-08-13 $41,871,000
6412091 Error correction system in a processing agent having minimal delay David L. Hill, Derek T. Bachand, Paul Breuder 2002-06-25 $55,737,000
6401172 Recycle mechanism for a processing agent Derek T. Bachand, David L. Hill 2002-06-04 $75,138,000
6378048 “SLIME” cache coherency system for agents with multi-layer caches Paul Breuder, Quinn W. Merrill, Derek T. Bachand, Harish Kumar, Brent E. Lince 2002-04-23 $65,430,000
6269465 Error correction system in a processing agent having minimal delay David L. Hill, Derek T. Bachand, Paul Breuder 2001-07-31 $265,780,000
6216208 Prefetch queue responsive to read request sequences Robert Greiner, David L. Hill, Derek T. Bachand, Matthew A. Fisch 2001-04-10 $109,826,000
6209068 Read line buffer and signaling protocol for processor David L. Hill, Derek T. Bachand, Matthew A. Fisch 2001-03-27 $117,605,000
6078981 Transaction stall technique to prevent livelock in multiple-processor systems David L. Hill, Derek T. Bachand, Paul Breuder, Matthew A. Fisch 2000-06-20 $289,858,000