| 9457821 |
Railroad signaling and communication system using a fail-safe voltage sensor to verify trackside conditions in safety-critical railroad applications |
Francois P. Pretorius, Charles A. Wisniewski, Lawrence Lowe |
2016-10-04 |
$20,436,000 |
| 8989926 |
Railroad signaling and communication system using a fail-safe voltage sensor to verify trackside conditions in safety-critical railroad applications |
Francois P. Pretorius, Lawrence Lowe, Charles A. Wisniewski |
2015-03-24 |
|
| 8205111 |
Communicating via an in-die interconnect |
Robert Greiner, Tim Frodsham, Derek T. Bachand, Anant Deval, Mark Waggoner |
2012-06-19 |
$20,138,000 |
| 7783809 |
Virtualization of pin functionality in a point-to-point interface |
Keshavan Tiruvallur, David I. Poisner, Herbert Hum, Frank Binns, Robert Greiner +1 more |
2010-08-24 |
$13,244,000 |
| 7487305 |
Prioritized bus request scheduling mechanism for processing devices |
Derek T. Bachand |
2009-02-03 |
$17,091,000 |
| 7363474 |
Method and apparatus for suspending execution of a thread until a specified memory access occurs |
Dion Rodgers, Deborah T. Marr, Shiv Kaushik, James B. Crossland, David A. Koufaty |
2008-04-22 |
$13,499,000 |
| 7143242 |
Dynamic priority external transaction system |
Derek T. Bachand, Chinna Prudvi, Deborah T. Marr |
2006-11-28 |
$16,743,000 |
| 7133981 |
Prioritized bus request scheduling mechanism for processing devices |
Derek T. Bachand |
2006-11-07 |
$13,207,000 |
| 7127561 |
Coherency techniques for suspending execution of a thread until a specified memory access occurs |
Deborah T. Marr, Dion Rodgers, Shiv Kaushik, James B. Crossland, David A. Koufaty |
2006-10-24 |
$13,658,000 |
| 6925556 |
Method and system to determine the bootstrap processor from a plurality of operable processors |
Frank Binns |
2005-08-02 |
$20,766,000 |
| 6907487 |
Enhanced highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2005-06-14 |
$24,999,000 |
| 6880031 |
Snoop phase in a highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2005-04-12 |
$19,475,000 |
| 6807592 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2004-10-19 |
$58,589,000 |
| 6804735 |
Response and data phases in a highly pipelined bus architecture |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2004-10-12 |
$44,708,000 |
| 6782457 |
Prioritized bus request scheduling mechanism for processing devices |
Derek T. Bachand |
2004-08-24 |
$22,522,000 |
| 6759359 |
Processes for producing a bleaching clay product |
Christian Fabry, Jorge Bello |
2004-07-06 |
|
| 6742085 |
Prefetch queue |
Chlnna B. Prudvi |
2004-05-25 |
$32,256,000 |
| 6735675 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Paul Breuder, Derek T. Bachand, Chinna Prudvi |
2004-05-11 |
$33,328,000 |
| 6732242 |
External bus transaction scheduling system |
Paul Breuder, Robert Greiner, Derek T. Bachand |
2004-05-04 |
$23,705,000 |
| 6696283 |
Particulate of sulfur-containing ore materials and heap made therefrom |
James A. Brierley |
2004-02-24 |
$140,452,000 |
| 6654837 |
Dynamic priority external transaction system |
Derek T. Bachand, Chinna Prudvi, Deborah T. Marr |
2003-11-25 |
$50,228,000 |
| 6609171 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2003-08-19 |
$57,835,000 |
| 6606692 |
Prioritized bus request scheduling mechanism for processing devices |
Derek T. Bachand |
2003-08-12 |
$56,289,000 |
| 6601121 |
Quad pumped bus architecture and protocol |
Gurbir Singh, Robert Greiner, Stephen S. Pawlowski, Donald D. Parker |
2003-07-29 |
$49,479,000 |
| 6578114 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Paul Breuder, Derek T. Bachand, Chinna Prudvi |
2003-06-10 |
$73,878,000 |
