Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332803 | Memory controller architecture | Emanuele Confalonieri, Patrick Estep | 2025-06-17 |
| 12282433 | Cache bypass | Emanuele Confalonieri, Patrick Estep, Nicola Del Gatto | 2025-04-22 |
| 12093566 | Memory controller for managing raid information | Nicola Del Gatto, Emanuele Confalonieri, Paolo Amato, Patrick Estep | 2024-09-17 |
| 11942175 | Memory device protection using interleaved multibit symbols | Paolo Amato, Marco Sforzin | 2024-03-26 |
| 11461011 | Extended line width memory-side cache systems and methods | Richard C. Murphy, Anton Korzh | 2022-10-04 |
| 11404136 | Memory device protection using interleaved multibit symbols | Paolo Amato, Marco Sforzin | 2022-08-02 |
| 11086526 | Adaptive line width cache systems and methods | Richard C. Murphy, Anton Korzh | 2021-08-10 |
| 10831377 | Extended line width memory-side cache systems and methods | Richard C. Murphy, Anton Korzh | 2020-11-10 |
| 10691347 | Extended line width memory-side cache systems and methods | Richard C. Murphy, Anton Korzh | 2020-06-23 |
| 10146657 | Initialization trace of a computing device | Robert C. Swanson, C. Brendan S. Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley +8 more | 2018-12-04 |
| 9547615 | Peripheral protocol negotiation | Dennis Bell | 2017-01-17 |
| 7831819 | Filter micro-coded accelerator | Anthony L. Chun, Lee Snyder, Ernest Tsui, Siva Simanapalli | 2010-11-09 |
| RE40921 | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system | William S. Wu, Peter D. MacWilliams, Muthurajan Jayakumar | 2009-09-22 |
| 7519344 | Bandpass amplifier, method, and system | Luiz M. Franca-Neto | 2009-04-14 |
| 6907487 | Enhanced highly pipelined bus architecture | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2005-06-14 |
| 6880031 | Snoop phase in a highly pipelined bus architecture | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2005-04-12 |
| 6807592 | Quad pumped bus architecture and protocol | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2004-10-19 |
| 6804735 | Response and data phases in a highly pipelined bus architecture | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2004-10-12 |
| RE38388 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Michael W. Rhodehamel | 2004-01-13 |
| 6609171 | Quad pumped bus architecture and protocol | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2003-08-19 |
| 6601121 | Quad pumped bus architecture and protocol | Gurbir Singh, Robert Greiner, David L. Hill, Donald D. Parker | 2003-07-29 |
| 6594756 | Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor | Sham M. Datta, Mani Ayyar, Douglas R. Moran | 2003-07-15 |
| 6557071 | Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage | Patrick F. Stolt | 2003-04-29 |
| 6487655 | Computer system formed with a processor and a system board provided with complementary initialization support | Frank L. Wildgrube | 2002-11-26 |
| 6446154 | Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture | Jasmin Ajanovic, Robert Greiner | 2002-09-03 |