Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423230 | Controller cache architeture | Emanuele Confalonieri | 2025-09-23 |
| 12299331 | Managed memory systems with multiple priority queues | Massimiliano Patriarca, Antonino Caprì, Emanuele Confalonieri, Angelo Alberto Rovelli | 2025-05-13 |
| 12282433 | Cache bypass | Emanuele Confalonieri, Patrick Estep, Stephen S. Pawlowski | 2025-04-22 |
| 12210771 | Arbitration policy to prioritize read command dequeuing by delaying write command dequeuing | — | 2025-01-28 |
| 12164774 | Performance throttling module | Federica Cresci, Emanuele Confanolieri | 2024-12-10 |
| 12164773 | Controller architecture for reliability, availability, serviceability access | Emanuele Confalonieri, Antonino Caprì, Federica Cresci, Massimiliano Turconi | 2024-12-10 |
| 12124729 | Controller to alter systems based on metrics and telemetry | Federica Cresci, Emanuele Confalonieri | 2024-10-22 |
| 12105971 | Dual-level refresh management | Niccolò Izzo | 2024-10-01 |
| 12093566 | Memory controller for managing raid information | Emanuele Confalonieri, Paolo Amato, Patrick Estep, Stephen S. Pawlowski | 2024-09-17 |
| 12086459 | Optimized control of the commands running in a cache | — | 2024-09-10 |
| 12039172 | Managing performance throttling in a digital controller | Federica Cresci, Emanuele Confanolieri | 2024-07-16 |
| 11989088 | Read data path | Emanuele Confalonieri | 2024-05-21 |
| 11977769 | Control of back pressure based on a total number of buffered read and write entries | — | 2024-05-07 |
| 11954035 | Cache architectures with address delay registers for memory devices | — | 2024-04-09 |
| 11934270 | Write command execution for data protection and recovery schemes | Marco Sforzin, Paolo Amato | 2024-03-19 |
| 11914893 | Managed memory systems with multiple priority queues | Massimiliano Patriarca, Antonino Caprì, Emanuele Confalonieri, Angelo Alberto Rovelli | 2024-02-27 |
| 11886749 | Interrupt mode or polling mode for memory devices | Federica Cresci, Massimiliano Turconi, Massimiliano Patriarca | 2024-01-30 |
| 11763887 | Cleaning memory blocks using multiple types of write operations | — | 2023-09-19 |
| 11720284 | Low latency storage based on data size | Federica Cresci, Massimiliano Patriarca, Maddalena Calzolari, Michela Spagnolo, Massimiliano Turconi | 2023-08-08 |
| 11561733 | Interrupt mode or polling mode for memory devices | Federica Cresci, Massimiliano Turconi, Massimiliano Patriarca | 2023-01-24 |
| 11481330 | Cache architectures with address delay registers for memory devices | — | 2022-10-25 |
| 11468948 | Cleaning memory blocks using multiple types of write operations | — | 2022-10-11 |
| 7750656 | Circuit for distributing a test signal applied to a pad of an electronic device | Antonio Geraci, Marco Sforzin, Nicola Rosito | 2010-07-06 |
| 7706193 | Voltage regulator for the programming circuit of a memory cell | Davide Cascone, Emanuele Confalonieri, Massimiliano Mollichelli | 2010-04-27 |
| 7596023 | Memory device employing three-level cells and related methods of managing | Alessandro Magnavacca, Massimiliano Scotti, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli | 2009-09-29 |