Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MS

Marco Sforzin — 123 Patents

Micron: 112 patents #127 of 6,374Top 2%
SSStmicroelectronics Sa: 9 patents #682 of 4,662Top 15%
PMPolitecnico Di Milano: 1 patents #126 of 476Top 30%
Boise, ID: #57 of 3,546 inventorsTop 2%
Idaho: #75 of 8,810 inventorsTop 1%
Overall (All Time): #9,462 of 4,157,543Top 1%
123 Patents All Time
Marco Sforzin has been granted 123 US patents while listed as an inventor at Micron. The first was granted in 2002 and the most recent in December 2025. Marco Sforzin ranks #9,462 of 4,157,543 US inventors in our database (top 0.23%). Patent records list Marco Sforzin in Boise, ID, US.

Patents per Year

Patents granted per year, 2002 to 2025Bar chart with a peak of 24 patents in 2024.peak 242002: 1 patents20022004: 1 patents2005: 3 patents20052008: 3 patents2010: 1 patents20102011: 1 patents2012: 1 patents20122013: 1 patents2014: 6 patents20142015: 3 patents2016: 1 patents20162017: 3 patents2018: 3 patents20182019: 3 patents2020: 14 patents20202021: 10 patents2022: 13 patents20222023: 13 patents2024: 24 patents20242025: 18 patents2025

Issued Patents All Time

Showing 1–25 of 123 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12511205 Memory failure prediction and mitigation Su Wei Lim, Senthil Thangaraj, Daniele Balluchi, Massimiliano Patriarca, Giorgio Servalli +5 more 2025-12-30
12499009 Interleaved Reed-Solomon (IRS) with collaborative decoding Joseph M. McCrate, Kirthi Shenoy, Brian M. Twait 2025-12-16
12468598 Decoder for burst correction read Solomon decoding for memory applications Joseph M. McCrate, Kirthi Shenoy, Brian M. Twait 2025-11-11
12461821 Low cost high performance LRAID 2025-11-04
12461820 Variable-length locked-raid for CXL devices with compression 2025-11-04
12405852 Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative Joseph M. McCrate, Kirthi Shenoy, Brian M. Twait 2025-09-02
12393524 Address scrambling by linear maps in Galois fields Federica Cresci 2025-08-19
12379993 Memory bank protection Paolo Amato, Daniele Balluchi 2025-08-05
12354653 Drift compensation for codewords in memory Paolo Amato, Luca Barletta, Marco Ferrari, Antonino Favano 2025-07-08
12321229 Burst correction reed solomon decoding for memory applications Joseph M. McCrate, Kirthi Shenoy, Brian M. Twait 2025-06-03
12277967 Memory device and method for operating the same including setting a recovery voltage Paolo Amato, Innocenzo Tortorelli 2025-04-15
12277969 Auto-referenced memory cell read techniques Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando 2025-04-15
12244324 Iterative error correction in memory systems Di-Hsien Ngu 2025-03-04
12235722 Apparatus for redundant array of independent disks Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri 2025-02-25
12222803 Intra-controllers for error correction code John D. Porter 2025-02-11
12222806 Cache line data protection Paolo Amato 2025-02-11
12210413 Data correction scheme with reduced device overhead Joseph M. McCrate, Paolo Amato, Lingming Yang, Nevil N. Gajera 2025-01-28
12189478 CRC RAID recovery from hard failure in memory systems Paolo Amato, Daniele Balluchi 2025-01-07
12154655 Adjustable memory cell reliability management Daniele Balluchi 2024-11-26 $57,813,000
12136456 Drift compensation for codewords in memory Paolo Amato, Luca Barletta, Marco Ferrari, Antonino Favano 2024-11-05 $88,145,000
12112057 Strategic memory cell reliability management Daniele Balluchi 2024-10-08 $26,633,000
12099457 Controller for managing multiple types of memory Emanuele Confalonieri, Daniele Balluchi, Paolo Amato, Danilo Caraccio 2024-09-24 $58,106,000
12100438 Methods, devices and systems for an improved management of a non-volatile memory Dionisio Minopoli, Daniele Balluchi 2024-09-24 $58,106,000
12087391 Drift compensation for codewords in memory Paolo Amato, Luca Barletta, Marco Ferrari, Antonino Favano 2024-09-10 $19,817,000
12088322 Method and system for on-ASIC error control decoding Paolo Amato 2024-09-10 $19,817,000