JM

Joseph M. McCrate

Micron: 14 patents #1,151 of 6,345Top 20%
Overall (All Time): #330,481 of 4,157,543Top 8%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12405852 Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative Kirthi Shenoy, Marco Sforzin, Brian M. Twait 2025-09-02
12321229 Burst correction reed solomon decoding for memory applications Kirthi Shenoy, Marco Sforzin, Brian M. Twait 2025-06-03
12316349 Iterative decoding technique for correcting DRAM device failures Nevil N. Gajera, Mohammed Ebrahim Hargan 2025-05-27
12210413 Data correction scheme with reduced device overhead Marco Sforzin, Paolo Amato, Lingming Yang, Nevil N. Gajera 2025-01-28
12170531 Iterative decoder for correcting dram device failures Nevil N. Gajera, Mohammed Ebrahim Hargan 2024-12-17
12072766 Data protection and recovery Marco Sforzin, Paolo Amato 2024-08-27
12020743 Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages Robert J. Gleixner, Hari Giduturi, Ramin Ghodsi 2024-06-25
11962327 Iterative decoding technique for correcting DRAM device failures Nevil N. Gajera, Mohammed Ebrahim Hargan 2024-04-16
11868211 Error detection and correction in memory Robert J. Gleixner 2024-01-09
11711987 Memory electrodes and formation thereof Robert J. Gleixner 2023-07-25
11605418 Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages Robert J. Gleixner, Hari Giduturi, Ramin Ghodsi 2023-03-14
11455210 Error detection and correction in memory Robert J. Gleixner 2022-09-27
11367483 Techniques for applying multiple voltage pulses to select a memory cell Josephine T. Hamada, Mingdong Cui, Karthik Sarpatwari, Jessica Chen 2022-06-21
10867671 Techniques for applying multiple voltage pulses to select a memory cell Josephine T. Hamada, Mingdong Cui, Karthik Sarpatwari, Jessica Chen 2020-12-15