Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362013 | Pre-decoder circuitry | Vijayakrishna J. Vankayala, Hari Giduturi, Jeffrey E. Koelling, Ramachandra Rao Jogu | 2025-07-15 |
| 12308070 | Word line drivers for multiple-die memory devices | Fatma Arzum Simsek-Ege | 2025-05-20 |
| 12176020 | Structures for word line multiplexing in three-dimensional memory arrays | Fatma Arzum Simsek-Ege, Richard E. Fackenthal | 2024-12-24 |
| 12131794 | Structures for word line multiplexing in three-dimensional memory arrays | Fatma Arzum Simsek-Ege, Richard E. Fackenthal | 2024-10-29 |
| 12057178 | Cell voltage drop compensation circuit | Kijun Nam | 2024-08-06 |
| 12051459 | Word line drivers for multiple-die memory devices | Fatma Arzum Simsek-Ege | 2024-07-30 |
| 11990176 | Pre-decoder circuity | Jin Seung Son | 2024-05-21 |
| 11984150 | Word line drivers for multiple-die memory devices | Fatma Arzum Simsek-Ege | 2024-05-14 |
| 11967373 | Pre-decoder circuitry | Vijayakrishna J. Vankayala, Hari Giduturi, Jeffrey E. Koelling, Ramachandra Rao Jogu | 2024-04-23 |
| 11798622 | Refresh operation of a memory cell | Joemar Sinipete, John Christopher Sancon | 2023-10-24 |
| 11776625 | Boost-assisted memory cell selection in a memory array | Hongmei Wang, Hari Giduturi | 2023-10-03 |
| 11710528 | Data-based polarity write operations | Karthik Sarpatwari, Nevil N. Gajera, Hongmei Wang | 2023-07-25 |
| 11605425 | Mux decoder with polarity transition capability | Nathan Joseph Sirocka, Jeffrey E. Koelling | 2023-03-14 |
| 11587635 | Selective inhibition of memory | Hongmei Wang, Nevil N. Gajera, Fabio Pellizzer | 2023-02-21 |
| 11587614 | Read spike mitigation in integrated circuit memory | Josephine T. Hamada, Kenneth Richard Surdyk, Lingming Yang | 2023-02-21 |
| 11527286 | Voltage drivers with reduced power consumption during polarity transition | Nathan Joseph Sirocka, Hari Giduturi | 2022-12-13 |
| 11430518 | Conditional drift cancellation operations in programming memory cells to store data | Hongmei Wang, Nevil N. Gajera | 2022-08-30 |
| 11404120 | Refresh operation of a memory cell | Joemar Sinipete, John Christopher Sancon | 2022-08-02 |
| 11380394 | Voltage profile for reduction of read disturb in memory cells | Hongmei Wang, Michel Ibrahim Ishac | 2022-07-05 |
| 11367483 | Techniques for applying multiple voltage pulses to select a memory cell | Josephine T. Hamada, Joseph M. McCrate, Karthik Sarpatwari, Jessica Chen | 2022-06-21 |
| 11183237 | Timing control of voltage supply during polarity transition | Nathan Joseph Sirocka, Byung S. Moon, Jeffrey E. Koelling | 2021-11-23 |
| 11139034 | Data-based polarity write operations | Karthik Sarpatwari, Nevil N. Gajera, Hongmei Wang | 2021-10-05 |
| 11133056 | Two-stage signaling for voltage driver coordination in integrated circuit memory devices | Nathan Joseph Sirocka | 2021-09-28 |
| 11114156 | Read spike mitigation in integrated circuit memory | Josephine T. Hamada, Kenneth Richard Surdyk, Lingming Yang | 2021-09-07 |
| 11087838 | Voltage drivers with reduced power consumption during polarity transition | Nathan Joseph Sirocka, Hari Giduturi | 2021-08-10 |