Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362013 | Pre-decoder circuitry | Vijayakrishna J. Vankayala, Hari Giduturi, Mingdong Cui, Ramachandra Rao Jogu | 2025-07-15 |
| 12051463 | Decoder architecture for memory device | Ferdinando Bedeschi, Hari Giduturi, Riccardo Muzzetto, Corrado Villa | 2024-07-30 |
| 11967373 | Pre-decoder circuitry | Vijayakrishna J. Vankayala, Hari Giduturi, Mingdong Cui, Ramachandra Rao Jogu | 2024-04-23 |
| 11605425 | Mux decoder with polarity transition capability | Nathan Joseph Sirocka, Mingdong Cui | 2023-03-14 |
| 11398276 | Decoder architecture for memory device | Ferdinando Bedeschi, Hari Giduturi, Riccardo Muzzetto, Corrado Villa | 2022-07-26 |
| 11217295 | Apparatuses and methods for address detection | Kallol Mazumder, Jason M. Brown, Derek R. May, Roger D. Norwood | 2022-01-04 |
| 11183237 | Timing control of voltage supply during polarity transition | Mingdong Cui, Nathan Joseph Sirocka, Byung S. Moon | 2021-11-23 |
| 11074970 | Mux decoder with polarity transition capability | Nathan Joseph Sirocka, Mingdong Cui | 2021-07-27 |
| 11031405 | Peripheral logic circuits under DRAM memory arrays | Mansour Fardad, Harish N. Venkata | 2021-06-08 |
| 10847222 | Timing control of voltage supply during polarity transition | Mingdong Cui, Nathan Joseph Sirocka, Byung S. Moon | 2020-11-24 |
| 10608621 | Per lane duty cycle correction | Gary L. Howe | 2020-03-31 |
| 10534686 | Apparatuses and methods for address detection | Kallol Mazumder, Jason M. Brown, Derek R. May, Roger D. Norwood | 2020-01-14 |
| 7323727 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2008-01-29 |
| 7211842 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2007-05-01 |
| 6967371 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2005-11-22 |
| 6952371 | Method of programming a programmable element in a memory device | Timothy B. Cowles | 2005-10-04 |
| 6933769 | Bandgap reference circuit | — | 2005-08-23 |
| 6831317 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2004-12-14 |
| 6815742 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2004-11-09 |
| 6807113 | Clamping circuit for the VPOP voltage used to program antifuses | Timothy B. Cowles | 2004-10-19 |
| 6657905 | Clamping circuit for the Vpop voltage used to program antifuses | Timothy B. Cowles | 2003-12-02 |
| 6624685 | Level detection by voltage addition/subtraction | Albert Shih | 2003-09-23 |
| 6512257 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2003-01-28 |
| 6400213 | Level detection by voltage addition/subtraction | Albert Shih | 2002-06-04 |
| 6396088 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2002-05-28 |