Issued Patents All Time
Showing 25 most recent of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412626 | Accessing memory cells in a vertical memory array | Paolo Fantini, Stefan Frederik Schippers, Lorenzo Fratin | 2025-09-09 |
| 12360741 | Multiply operation circuit, multiply and accumulate circuit, and methods thereof | Stefano Sivero | 2025-07-15 |
| 12165730 | Providing power availability information to memory | Graziano Mirichigni | 2024-12-10 |
| 12086421 | Memory device with data scrubbing capability and methods | Graziano Mirichigni, Andrea Martinelli, Christophe Vincent Antoine Laurent | 2024-09-10 |
| 12051463 | Decoder architecture for memory device | Ferdinando Bedeschi, Jeffrey E. Koelling, Hari Giduturi, Riccardo Muzzetto | 2024-07-30 |
| 11961588 | Variable page size architecture | — | 2024-04-16 |
| 11948651 | Wordline capacitance balancing | Shane D. Moser | 2024-04-02 |
| 11887664 | Systems and methods for adaptive self-referenced reads of memory devices | Graziano Mirichigni | 2024-01-30 |
| 11877457 | Vertical 3D memory device and accessing method | Paolo Fantini, Stefan Frederik Schippers, Efrem Bolandrina | 2024-01-16 |
| 11818902 | Vertical 3D memory device and method for manufacturing the same | Paolo Fantini, Paolo Tessariol | 2023-11-14 |
| 11749316 | Providing power availability information to memory | Graziano Mirichigni | 2023-09-05 |
| 11735255 | Voltage equalization for pillars of a memory array | Ferdinando Bedeschi, Paolo Fantini | 2023-08-22 |
| 11651809 | Access schemes for activity-based data protection in a memory device | Andrea Martinelli | 2023-05-16 |
| 11538522 | Systems and methods for adaptive self-referenced reads of memory devices | Graziano Mirichigni | 2022-12-27 |
| 11462289 | Wordline capacitance balancing | Shane D. Moser | 2022-10-04 |
| 11437097 | Voltage equalization for pillars of a memory array | Ferdinando Bedeschi, Paolo Fantini | 2022-09-06 |
| 11398276 | Decoder architecture for memory device | Ferdinando Bedeschi, Jeffrey E. Koelling, Hari Giduturi, Riccardo Muzzetto | 2022-07-26 |
| 11250889 | Providing power availability information to memory | Graziano Mirichigni | 2022-02-15 |
| 11244713 | Variable page size architecture | — | 2022-02-08 |
| 11222680 | Memory plate segmentation to reduce operating power | Tae H. Kim | 2022-01-11 |
| 11205469 | Power domain switches for switching power reduction | Stefan Frederik Schippers, Christophe Vincent Antoine Laurent | 2021-12-21 |
| 11158673 | Vertical 3D memory device and method for manufacturing the same | Paolo Fantini, Paolo Tessariol | 2021-10-26 |
| 10998074 | Wordline capacitance balancing | Shane D. Moser | 2021-05-04 |
| 10991411 | Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations | Andrea Martinelli | 2021-04-27 |
| 10915321 | Apparatuses and methods for memory operations having variable latencies | Graziano Mirichigni, Luca Porzio, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth | 2021-02-09 |