Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340832 | Circuitry borrowing for memory arrays | Francesco Mastroianni, Kiyoshi Nakai | 2025-06-24 |
| 12300305 | Parallel access in a memory array | Efrem Bolandrina, Christophe Vincent Antoine Laurent, Ferdinando Bedeschi | 2025-05-13 |
| 12260907 | Shared decoder architecture for three-dimensional memory arrays | Christophe Vincent Antoine Laurent, Efrem Bolandrina, Ferdinando Bedeschi | 2025-03-25 |
| 12228991 | Architecture-based power management for a memory device | Christophe Vincent Antoine Laurent, Graziano Mirichigni | 2025-02-18 |
| 12182432 | Circuit partitioning for a memory device | Christophe Vincent Antoine Laurent, Claudio Nava, Marco Defendi | 2024-12-31 |
| 12158914 | User interfaces for refining video group packages | Masoud Loghmani, Roland Peter Kehl, Bernhard Suter, Daniel Cotting, Dan Filimon | 2024-12-03 |
| 12114044 | Digital video analysis | Masoud Loghmani, Roland Peter Kehl, Bernhard Suter, Daniel Cotting, Dan Filimon | 2024-10-08 |
| 12086421 | Memory device with data scrubbing capability and methods | Graziano Mirichigni, Corrado Villa, Christophe Vincent Antoine Laurent | 2024-09-10 |
| 12045113 | Bank configurable power modes | Graziano Mirichigni, Christophe Vincent Antoine Laurent | 2024-07-23 |
| 12002510 | Program current controller and sense circuit for cross-point memory devices | Andrea Ghetti, Efrem Bolandrina, Ferdinando Bedeschi, Paolo Fantini | 2024-06-04 |
| 11967372 | Shared decoder architecture for three-dimensional memory arrays | Christophe Vincent Antoine Laurent, Efrem Bolandrina, Ferdinando Bedeschi | 2024-04-23 |
| 11948638 | Techniques for parallel memory cell access | Paolo Fantini, Maurizio Rizzi | 2024-04-02 |
| 11915740 | Parallel access in a memory array | Efrem Bolandrina, Christophe Vincent Antoine Laurent, Ferdinando Bedeschi | 2024-02-27 |
| 11830570 | Input/output line sharing for memory arrays | Christopher Vincent Antoine Laurent | 2023-11-28 |
| 11804264 | Decoding architecture for memory tiles | Paolo Fantini, Claudio Nava | 2023-10-31 |
| 11740678 | Architecture-based power management for a memory device | Christophe Vincent Antoine Laurent, Graziano Mirichigni | 2023-08-29 |
| 11733913 | Balancing data for storage in a memory device | Christophe Vincent Antoine Laurent, Marco Sforzin, Paolo Amato | 2023-08-22 |
| 11651809 | Access schemes for activity-based data protection in a memory device | Corrado Villa | 2023-05-16 |
| 11475947 | Decoding architecture for memory tiles | Paolo Fantini, Claudio Nava | 2022-10-18 |
| 11262937 | Balancing data for storage in a memory device | Christophe Vincent Antoine Laurent, Marco Sforzin, Paolo Amato | 2022-03-01 |
| 11243596 | Architecture-based power management for a memory device | Christophe Vincent Antoine Laurent, Graziano Mirichigni | 2022-02-08 |
| 11217291 | Circuitry borrowing for memory arrays | Francesco Mastroianni, Kiyoshi Nakai | 2022-01-04 |
| 11152039 | Input/output line sharing for memory arrays | Christophe Vincent Antoine Laurent | 2021-10-19 |
| 11144228 | Circuit partitioning for a memory device | Christophe Vincent Antoine Laurent, Claudio Nava, Marco Defendi | 2021-10-12 |
| 10991411 | Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations | Corrado Villa | 2021-04-27 |