Issued Patents All Time
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321610 | Balanced codewords for reducing a selected state in memory cells | Riccardo Muzzetto | 2025-06-03 |
| 12300305 | Parallel access in a memory array | Efrem Bolandrina, Andrea Martinelli, Ferdinando Bedeschi | 2025-05-13 |
| 12288592 | Performing sense operations in memory | Michele Maria Venturini, Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto, Christian Caillat | 2025-04-29 |
| 12288591 | Memory device having an improved ECC architecture | Riccardo Muzzetto | 2025-04-29 |
| 12266410 | Methods and systems for improving ECC operation of memories | Riccardo Muzzetto | 2025-04-01 |
| 12260907 | Shared decoder architecture for three-dimensional memory arrays | Andrea Martinelli, Efrem Bolandrina, Ferdinando Bedeschi | 2025-03-25 |
| 12228991 | Architecture-based power management for a memory device | Andrea Martinelli, Graziano Mirichigni | 2025-02-18 |
| 12182432 | Circuit partitioning for a memory device | Andrea Martinelli, Claudio Nava, Marco Defendi | 2024-12-31 |
| 12135610 | ECC configuration in memories | Graziano Mirichigni, Riccardo Muzzetto | 2024-11-05 |
| 12086421 | Memory device with data scrubbing capability and methods | Graziano Mirichigni, Corrado Villa, Andrea Martinelli | 2024-09-10 |
| 12079082 | Methods and systems for managing memory with dynamic ECC protection | Riccardo Muzzetto | 2024-09-03 |
| 12068016 | Unbalanced programmed data states in memory | Riccardo Muzzetto | 2024-08-20 |
| 12045113 | Bank configurable power modes | Graziano Mirichigni, Andrea Martinelli | 2024-07-23 |
| 12039176 | Providing multiple error correction code protection levels in memory | Marco Sforzin, Riccardo Muzzetto | 2024-07-16 |
| 11967372 | Shared decoder architecture for three-dimensional memory arrays | Andrea Martinelli, Efrem Bolandrina, Ferdinando Bedeschi | 2024-04-23 |
| 11915740 | Parallel access in a memory array | Efrem Bolandrina, Andrea Martinelli, Ferdinando Bedeschi | 2024-02-27 |
| 11914476 | Generating a protected and balanced codeword | — | 2024-02-27 |
| 11811424 | Fixed weight codewords for ternary memory cells | Riccardo Muzzetto | 2023-11-07 |
| 11740678 | Architecture-based power management for a memory device | Andrea Martinelli, Graziano Mirichigni | 2023-08-29 |
| 11742047 | Shared error correction coding circuitry | Marco Sforzin, Paolo Amato | 2023-08-29 |
| 11733913 | Balancing data for storage in a memory device | Andrea Martinelli, Marco Sforzin, Paolo Amato | 2023-08-22 |
| 11687411 | Generating a balanced codeword protected by an error correction code | — | 2023-06-27 |
| 11567831 | Generating a protected and balanced codeword | — | 2023-01-31 |
| 11494264 | Generating a protected and balanced codeword | — | 2022-11-08 |
| 11355162 | Active boundary quilt architecture memory | — | 2022-06-07 |