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Apparatus configured to program memory cells using an intermediate level for multiple data states |
Carmine Miccoli, Akira Goda |
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Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND |
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Erasing memory segments in a memory block of memory cells using select gate control line voltages |
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Apparatus configured to program memory cells using an intermediate level for multiple data states |
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Programming memory cells to be programmed to different levels to an intermediate level from a lowest level |
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Erasing memory segments in a memory block of memory cells using select gate control line voltages |
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2017-10-03 |
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Programming memory cells to be programmed to different levels to an intermediate level from a lowest level |
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2017-04-25 |
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Method for manufacturing a dual work function semiconductor device |
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2016-01-26 |
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Techniques for providing a semiconductor memory device |
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2015-07-28 |
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Method for tuning the effective work function of a gate structure in a semiconductor device |
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Oxygen diffusion barrier comprising Ru |
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Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated-circuit component |
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MIS transistor and method for making same on a semiconductor substrate |
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