Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11031405 | Peripheral logic circuits under DRAM memory arrays | Harish N. Venkata, Jeffrey E. Koelling | 2021-06-08 |
| 10153007 | Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods | Harish N. Venkata, John F. Schreck | 2018-12-11 |
| 9224436 | Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods | Harish N. Venkata, John F. Schreck | 2015-12-29 |
| 6219294 | Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories | Brian W. Huber, Roger D. Norwood | 2001-04-17 |