Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6297671 | Level detection by voltage addition/subtraction | Albert Shih | 2001-10-02 |
| 6288925 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2001-09-11 |
| 6281760 | On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory | Wah Kit Loh | 2001-08-28 |
| 6259280 | Class AB amplifier for use in semiconductor memory devices | — | 2001-07-10 |
| 6240047 | Synchronous dynamic random access memory with four-bit data prefetch | J. Patrick Kawamura | 2001-05-29 |
| 6215718 | Architecture for large capacity high-speed random access memory | — | 2001-04-10 |
| 6140861 | Bias pump arrangement including a signal-transition-detection circuit | Ching-Yuh Tsay | 2000-10-31 |
| 6115279 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2000-09-05 |
| 6115321 | Synchronous dynamic random access memory with four-bit data prefetch | J. Patrick Kawamura | 2000-09-05 |
| 6069813 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 2000-05-30 |
| 6037762 | Voltage detector having improved characteristics | Yung-Che Albert Shih | 2000-03-14 |
| 6005822 | Bank selectable Y-decoder circuit and method of operation | Patrick Kawamura | 1999-12-21 |
| 5978254 | Semiconductor memory structure for improved charge storage | Hugh P. McAdams | 1999-11-02 |
| 5953242 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Troy H. Herndon | 1999-09-14 |
| 5945869 | Voltage detector using body effect | — | 1999-08-31 |
| 5802005 | Four bit pre-fetch sDRAM column select architecture | Masayuki Nakamura, Paulette Thurston, Hugh P. McAdams | 1998-09-01 |
| 5792682 | Method for reducing charge loss | Hugh P. McAdams | 1998-08-11 |
| 5696721 | Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range | Hugh P. McAdams | 1997-12-09 |
| 5623448 | Apparatus and method for implementing integrated circuit memory device component redundancy using dynamic power distribution switching | — | 1997-04-22 |
| 5600277 | Apparatus and method for a NMOS redundancy fuse passgate circuit using a VPP supply | — | 1997-02-04 |
| 5502671 | Apparatus and method for a semiconductor memory configuration-dependent output buffer supply circuit | Hugh P. McAdams | 1996-03-26 |