Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394755 | Inter-die signal load reduction technique in multi-die package | — | 2025-08-19 |
| 12362013 | Pre-decoder circuitry | Hari Giduturi, Jeffrey E. Koelling, Mingdong Cui, Ramachandra Rao Jogu | 2025-07-15 |
| 12333191 | Apparatus with calibration input mechanism and methods for operating the same | Kevin G. Werhane, Tyrel Z. Jensen | 2025-06-17 |
| 12321288 | Asymmetric read-write sequence for interconnected dies | Hyun Yoo Lee, Kang-Yong Kim, Jason McBride Brown, Venkatraghavan Bringivijayaraghavan | 2025-06-03 |
| 12261613 | Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device | — | 2025-03-25 |
| 12176031 | Divided clock transmission in a three-dimensional stacked memory device | Hari Giduturi, Jason M. Brown | 2024-12-24 |
| 12141084 | Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses | — | 2024-11-12 |
| 11996149 | Access command delay using delay locked loop (DLL) circuitry | Jason M. Brown | 2024-05-28 |
| 11967373 | Pre-decoder circuitry | Hari Giduturi, Jeffrey E. Koelling, Mingdong Cui, Ramachandra Rao Jogu | 2024-04-23 |
| 11955981 | Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device | — | 2024-04-09 |
| 11887687 | Read operations for a memory array and register | — | 2024-01-30 |
| 11810641 | Apparatuses and method for trimming input buffers based on identified mismatches | Christian Mohr, Jennifer E. Taylor | 2023-11-07 |
| 11762786 | Low power area efficient divided clock shifter scheme for high latency designs | — | 2023-09-19 |
| 11755506 | Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses | — | 2023-09-12 |
| 11742008 | Memory device with a clocking mechanism | Jason M. Brown, Todd A. Dauenbaugh | 2023-08-29 |
| 11727979 | Methods of reducing clock domain crossing timing violations, and related devices and systems | Kallol Mazumder, Navya Sri Sreeram, William C. Waldrop | 2023-08-15 |
| 11705429 | Redundant through-silicon vias | Jason M. Brown | 2023-07-18 |
| 11487610 | Methods for parity error alert timing interlock and memory devices and systems employing the same | William C. Waldrop, Scott E. Smith | 2022-11-01 |
| 11380395 | Access command delay using delay locked loop (DLL) circuitry | Jason M. Brown | 2022-07-05 |
| 11366772 | Separate inter-die connectors for data and error correction information and related systems, methods, and apparatuses | — | 2022-06-21 |
| 11334426 | CRC error alert synchronization | Thanh K. Mai | 2022-05-17 |
| 11164613 | Processing multi-cycle commands in memory devices, and related methods, devices, and systems | — | 2021-11-02 |
| 11127482 | Detection circuitry to detect a deck of a memory array | Bret Johnson | 2021-09-21 |
| 11094363 | Reduced peak self-refresh current in a memory device | — | 2021-08-17 |
| 11024349 | Memory device with a clocking mechanism | Jason M. Brown, Todd A. Dauenbaugh | 2021-06-01 |