Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223999 | Synchronous input buffer control using a write shifter | David R. Brown, Guy S. Perry | 2025-02-11 |
| 12183385 | Apparatuses and methods for a per-DRAM addressability synchronizer circuit | Liang Chen, Shingo Mitsubori, Ryo Fujimaki, Atsuko Momma | 2024-12-31 |
| 11996162 | Synchronous input buffer enable for DFE operation | Won Joo Yun | 2024-05-28 |
| 11727979 | Methods of reducing clock domain crossing timing violations, and related devices and systems | Kallol Mazumder, Navya Sri Sreeram, Vijayakrishna J. Vankayala | 2023-08-15 |
| 11495281 | Write interamble counter | Daniel B. Penney | 2022-11-08 |
| 11487610 | Methods for parity error alert timing interlock and memory devices and systems employing the same | Vijayakrishna J. Vankayala, Scott E. Smith | 2022-11-01 |
| 11417374 | Reset speed modulation circuitry for a decision feedback equalizer of a memory device | Gary L. Howe | 2022-08-16 |
| 11264078 | Metastable resistant latch | Daniel B. Penney | 2022-03-01 |
| 11145353 | Centralized DFE reset generator for a memory device | Daniel B. Penney | 2021-10-12 |
| 10872658 | Reduced shifter memory system | Jason M. Brown, Vijayakrishna J. Vankayala, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda | 2020-12-22 |
| 10838799 | Parallel error calculation | — | 2020-11-17 |
| 10840908 | Systems and methods for controlling semiconductor device wear | — | 2020-11-17 |
| 10783980 | Methods for parity error synchronization and memory devices and systems employing the same | Vijayakrishna J. Vankayala | 2020-09-22 |
| 10447267 | Systems and methods for controlling semiconductor device wear | — | 2019-10-15 |
| 10354717 | Reduced shifter memory system | Jason M. Brown, Vijayakrishna J. Vankayala, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda | 2019-07-16 |
| 10269441 | Systems and methods for threshold voltage modification and detection | Daniel B. Penney | 2019-04-23 |
| 10127994 | Systems and methods for threshold voltage modification and detection | Daniel B. Penney | 2018-11-13 |
| 9479361 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals | — | 2016-10-25 |
| 7915924 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals | — | 2011-03-29 |
| 7898294 | Pre-driver logic | Daniel B. Penney | 2011-03-01 |
| 7675324 | Pre-driver logic | Daniel B. Penney | 2010-03-09 |
| 7560956 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals | — | 2009-07-14 |
| 7230457 | Programmable dual drive strength output buffer with a shared boot circuit | — | 2007-06-12 |
| 6975149 | Method and circuit for adjusting the timing of output data based on an operational mode of output drivers | Vladimir Mikhalev, Aaron Schoenfeld, Daniel B. Penney | 2005-12-13 |
| 6885226 | Programmable dual-drive strength output buffer with a shared boot circuit | — | 2005-04-26 |