Issued Patents All Time
Showing 1–25 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423253 | Current-controlled buffer using analog bias | Bhargav Kalva | 2025-09-23 |
| 11996162 | Synchronous input buffer enable for DFE operation | William C. Waldrop | 2024-05-28 |
| 11922996 | Apparatuses, systems, and methods for ZQ calibration | Hyunui Lee | 2024-03-05 |
| 11886376 | Apparatus including reconfigurable interface and methods of manufacturing the same | Sang Hoon Shin | 2024-01-30 |
| 11855812 | Hybrid loop unrolled decision feedback equalizer architecture | Jennifer E. Taylor | 2023-12-26 |
| 11789835 | Test input/output speed conversion and related apparatuses and methods | Sang Hoon Shin, Rajesh H. Kariya | 2023-10-17 |
| 11677537 | Signal delay control and related apparatuses, systems, and methods | Hyunui Lee, Baekkyu Choi | 2023-06-13 |
| 11619964 | Methods for improving timing in memory devices, and related devices and systems | Hyunui Lee | 2023-04-04 |
| 10908212 | Semiconductor memory device including a shift register | Hyunui Lee, Hye-Seung Yu | 2021-02-02 |
| 10680593 | Delay locked loop circuit and method of operating a delay locked loop circuit | Sang-Kyeom Kim, Sukyong Kang, Ho Jun Chang | 2020-06-09 |
| 10651156 | Memory package and memory device utilizing an intermediate chip | Hye-Seung Yu, Hyun Ui Lee | 2020-05-12 |
| 10509070 | Short circuit detecting device of stacked memory chips and method thereof | Sukyong Kang, Hye-Seung Yu, Hyunui Lee | 2019-12-17 |
| 10078110 | Short circuit detecting device of stacked memory chips and method thereof | Sukyong Kang, Hye-Seung Yu, Hyunui Lee | 2018-09-18 |
| 9959935 | Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same | Sukyong Kang, Hye-Seung Yu, Hyun Ui Lee, Jae-Hun Jung | 2018-05-01 |
| 9870808 | Memory device for performing calibration operation | Hyunui Lee, Hye-Seung Yu, In-Dal Song | 2018-01-16 |
| 9654093 | Electronic device having a delay locked loop, and memory device having the same | Yong Shim | 2017-05-16 |
| 9501041 | Duty cycle error detection device and duty cycle correction device having the same | Yong Shim | 2016-11-22 |
| 9214202 | Input buffer and memory device including the same | Yong Shim, Seung-Jun Bae | 2015-12-15 |
| 8742806 | Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit | Hyun Woo Lee, Dong-Suk Shin | 2014-06-03 |
| 8390364 | Internal voltage generation circuit for semiconductor apparatus | Ki Han Kim, Hyun Woo Lee | 2013-03-05 |
| 8378726 | Clock signal duty correction circuit | Yong-Ju Kim, Dae-Han Kwon, Hae-Rang Choi, Jae-Min Jang | 2013-02-19 |
| 8350604 | Clock receiver in semiconductor integrated circuit and method of controlling the same | Hyun Woo Lee, Ki Han Kim | 2013-01-08 |
| 8237478 | DLL circuit having activation points | Hyun Woo Lee | 2012-08-07 |
| 8228104 | Duty cycle correcting circuit and method of correcting a duty cycle | Hyun Woo Lee | 2012-07-24 |
| 8154326 | Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit | Hyun Woo Lee, Dong-Suk Shin | 2012-04-10 |