Issued Patents All Time
Showing 25 most recent of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8516292 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Wen Li, R. Jacob Baker | 2013-08-20 |
| 8400868 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation | Ross Dermott | 2013-03-19 |
| 7983110 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation | Ross Dermott | 2011-07-19 |
| 7916821 | Method and apparatus for output data synchronization with system clock in DDR | Wen Li | 2011-03-29 |
| 7877623 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Wen Li, R. Jacob Baker | 2011-01-25 |
| 7729192 | Circuit and method for reducing power in a memory device during standby modes | — | 2010-06-01 |
| 7606101 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation | Ross Dermott | 2009-10-20 |
| 7519850 | Method and unit for buffer control | Debra M. Bell | 2009-04-14 |
| 7460429 | Circuit and method for reducing power in a memory device during standby modes | — | 2008-12-02 |
| 7421607 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Wen Li, R. Jacob Baker | 2008-09-02 |
| 7378723 | Method and apparatus for decoupling conductive portions of a microelectronic device package | David J. Corisis | 2008-05-27 |
| 7294790 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-11-13 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits | Vladimir Mikhalev | 2007-09-18 |
| 7257884 | Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration | David J. Corisis, Tyler Gomm | 2007-08-21 |
| 7248532 | Device, system and method for reducing power in a memory device during standby modes | — | 2007-07-24 |
| 7239152 | Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-07-03 |
| 7237136 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Wen Li, R. Jacob Baker | 2007-06-26 |
| 7212013 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-05-01 |
| 7208959 | Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-04-24 |
| 7208935 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-04-24 |
| 7199593 | Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2007-04-03 |
| 7183138 | Method and apparatus for decoupling conductive portions of a microelectronic device package | David J. Corisis | 2007-02-27 |
| 7155630 | Method and unit for selectively enabling an input buffer based on an indication of a clock transition | Debra M. Bell | 2006-12-26 |
| 7145323 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2006-12-05 |
| 7106646 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation | Ross Dermott | 2006-09-12 |