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Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
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Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
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Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
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Delay circuit with reset-based forward path static delay |
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Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
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Measure-controlled delay circuit with reduced playback error |
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Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
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Method and apparatus for determining digital delay line entry point |
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Method and apparatus for determining digital delay line entry point |
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