Issued Patents All Time
Showing 51–75 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6661717 | Dynamically centered setup-time and hold-time window | Tyler Gomm | 2003-12-09 |
| 6635560 | Method for implementing selected functionality on an integrated circuit device | — | 2003-10-21 |
| 6617692 | Apparatus for implementing selected functionality on an integrated circuit device | — | 2003-09-09 |
| 6605969 | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers | Vladimir Mikhalev, Daniel B. Penney, William C. Waldrop | 2003-08-12 |
| 6600215 | Method and apparatus for coupling a semiconductor die to die terminals | Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen | 2003-07-29 |
| 6579746 | Method and apparatus for coupling a semiconductor die to die terminals | Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen | 2003-06-17 |
| 6576987 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Jerry M. Brooks | 2003-06-10 |
| 6563299 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer | Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert | 2003-05-13 |
| 6556399 | Device and method for electrostatic discharge protection of a circuit device | Alan J. Wilson | 2003-04-29 |
| 6556489 | Method and apparatus for determining digital delay line entry point | Tyler Gomm, Travis E. Dirkes, Ross Dermott | 2003-04-29 |
| 6472764 | Method and apparatus for implementing selected functionality on an integrated circuit device | — | 2002-10-29 |
| 6462404 | Multilevel leadframe for a packaged integrated circuit | — | 2002-10-08 |
| 6396727 | Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same | Rajesh Somasekharan | 2002-05-28 |
| 6392458 | Method and apparatus for digital delay locked loop circuits | James E. Miller | 2002-05-21 |
| 6359482 | Method and apparatus for digital delay locked loop circuits | James E. Miller | 2002-03-19 |
| 6351040 | Method and apparatus for implementing selected functionality on an integrated circuit device | — | 2002-02-26 |
| 6348400 | Method and apparatus for implementing selected functionality on an integrated circuit device | — | 2002-02-19 |
| 6344976 | Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die | Jerry M. Brooks | 2002-02-05 |
| 6324657 | On-clip testing circuit and method for improving testing of integrated circuits | Wallace E. Fister | 2001-11-27 |
| 6316976 | Method and apparatus for improving the performance of digital delay locked loop circuits | James E. Miller, Manny K. F. Ma, R. Jacob Baker | 2001-11-13 |
| 6271582 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Jerry M. Brooks | 2001-08-07 |
| 6215172 | Grinding technique for integrated circuits | — | 2001-04-10 |
| 6181540 | Device and method for electrostatic discharge protection of a circuit device | Alan J. Wilson | 2001-01-30 |
| 6148509 | Method for supporting an integrated circuit die | Jerry M. Brooks | 2000-11-21 |
| 6137334 | Logic circuit delay stage and delay line utilizing same | James E. Miller | 2000-10-24 |