Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of reducing clock domain crossing timing violations, and related devices and systems

Methods of reducing clock domain crossing timing violations, and related devices and systems

US Patent 11727979 · Granted Aug 15, 2023

Estimated economic value: $9,169,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Data input buffer with a branched DFE reset path2025
Techniques for performing write operations2025
Apparatus operating in geardown mode2025
Apparatus operating in geardown mode2025
Repeater scheme for inter-die signals in multi-die package2025
Inter-die signal load reduction technique in multi-die package2025
Pre-decoder circuitry2025
Apparatus with calibration input mechanism and methods for operating the same2025
Asymmetric read-write sequence for interconnected dies2025
Apparatus including parallel pipelines and methods of manufacturing the same2025
Apparatus including parallel pipelines and methods of manufacturing the same2025
Divided quad clock-based inter-die clocking in a three-dimensional stacked memor2025