BM

Byung S. Moon

Micron: 15 patents #1,089 of 6,345Top 20%
Samsung: 8 patents #15,984 of 75,807Top 25%
Overall (All Time): #180,763 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12002537 Pre-decoder circuity Ramachandra Rao Jogu 2024-06-04
11183237 Timing control of voltage supply during polarity transition Mingdong Cui, Nathan Joseph Sirocka, Jeffrey E. Koelling 2021-11-23
11132142 Systems and methods for writing zeros to a memory array Harish N. Venkata, Gary L. Howe, Myung-Ho Bae 2021-09-28
11087820 Systems and methods for plate voltage regulation during memory array access Yu-Feng Chen, Myung-Ho Bae, Harish N. Venkata 2021-08-10
10872658 Reduced shifter memory system Jason M. Brown, Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Ravi Kiran Kandikonda 2020-12-22
10847222 Timing control of voltage supply during polarity transition Mingdong Cui, Nathan Joseph Sirocka, Jeffrey E. Koelling 2020-11-24
10825491 Systems and methods for writing zeros to a memory array Gary L. Howe, Harish N. Venkata, David R. Brown 2020-11-03
10795603 Systems and methods for writing zeros to a memory array Harish N. Venkata, Gary L. Howe, Myung-Ho Bae 2020-10-06
10790012 Memory with a reduced array data bus footprint Michael V. Ho 2020-09-29
10777236 Methods and apparatuses of driver circuits without voltage level shifters Tae H. Kim 2020-09-15
10504563 Methods and apparatuses of driver circuits without voltage level shifters Tae H. Kim 2019-12-10
10497424 Systems and methods for plate voltage regulation during memory array access Yu-Feng Chen, Myung-Ho Bae, Harish N. Venkata 2019-12-03
10402116 Systems and methods for writing zeros to a memory array Harish N. Venkata, Gary L. Howe, Myung-Ho Bae 2019-09-03
10366743 Memory with a reduced array data bus footprint Michael V. Ho 2019-07-30
10354717 Reduced shifter memory system Jason M. Brown, Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Ravi Kiran Kandikonda 2019-07-16
6762948 Semiconductor memory device having first and second memory architecture and memory system using the same Kye-hyun Kyun 2004-07-13
6636451 Semiconductor memory device internal voltage generator and internal voltage generating method Duk-Ha Park 2003-10-21
6414896 Semiconductor memory device having column redundancy scheme to improve redundancy efficiency Su-A Kim 2002-07-02
6366155 Reference voltage generators and methods including supplementary current generation, and integrated circuits including the same Mi Seon Kang, Ho-Sung Song 2002-04-02
6326833 Highly effective charge pump employing NMOS transistors 2001-12-04
6219298 High-speed address decoders and related address decoding methods Nak-won Hur 2001-04-17
6163498 Methods and systems for column line selection in a memory device 2000-12-19
6078536 Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods Kye-hyun Kyung, Sung Joo Lee 2000-06-20