Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163741 | Scribe lane structure in which pad including via hole is arranged on sawing line | Young-Ho Kim, Jeong-Sik Nam, Kyoung Min Kim, Tae-Hyeong Lee | 2018-12-25 |
| 10008247 | Memory device for performing multi-core access to bank groups | Tae Young Oh | 2018-06-26 |
| 9824946 | Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level | Young-Yong Byun, Chi-Wook Kim | 2017-11-21 |
| 9461656 | Injection-locked phase locked loop circuits using delay locked loops | Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Jeong-Don Ihm | 2016-10-04 |
| 9396771 | Memory device for performing multi-core access to bank groups | Tae Young Oh | 2016-07-19 |
| 9264039 | Circuit and method for on-die termination, and semiconductor memory device including the same | Ho-Seok Seol, Seung-Jun Bae, Young-Soo Sohn | 2016-02-16 |
| 9053774 | Duty cycle corrector and systems including the same | Ho-Seok Seol, Seung-Jun Bae | 2015-06-09 |
| 8027219 | Semiconductor memory devices having signal delay controller and methods performed therein | Jeong-Sik Nam | 2011-09-27 |
| 7599234 | Semiconductor memory devices having signal delay controller and methods performed therein | Jeong-Sik Nam | 2009-10-06 |
| 7319634 | Address converter semiconductor device and semiconductor memory device having the same | Chul-Hwan Choo | 2008-01-15 |
| 7027339 | Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof | Dong-Hak Shin, Byung-Sik Moon | 2006-04-11 |
| 6906963 | Semiconductor memory device having output driver for high frequency operation | Ki-Whan Song, Dong Su Lee | 2005-06-14 |
| 6756856 | Clock generation circuits and integrated circuit memory devices for controlling a clock period based on temperature and methods for using the same | Ki-Hwan Song | 2004-06-29 |
| 6577554 | Semiconductor memory device for providing margin of data setup time and data hold time of data terminal | Mi Seon Kang | 2003-06-10 |
| 6538337 | Ball grid array package for providing constant internal voltage via a PCB substrate routing configuration | — | 2003-03-25 |
| 6366155 | Reference voltage generators and methods including supplementary current generation, and integrated circuits including the same | Byung S. Moon, Mi Seon Kang | 2002-04-02 |
| 6310796 | Dynamic random access memory device and .mu.BGA package using multiple reference voltage pads | — | 2001-10-30 |
| 6239642 | Integrated circuits with variable signal line loading circuits and methods of operation thereof | Jong Sun Kim, Sung-Min Hwang | 2001-05-29 |
| 6178109 | Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise | Jei-Hwan Yoo | 2001-01-23 |
| 6121677 | Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers | Ki Jong Lee | 2000-09-19 |
| 6115311 | Semiconductor memory device capable of selecting a plurality of refresh cycle modes | Jong-Hyun Choi, Jun-Young Jyun | 2000-09-05 |
| 5959906 | Semiconductor memory device with a fully accessible redundant memory cell array | Jong-Hyun Choi | 1999-09-28 |