Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824946 | Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level | Young-Yong Byun, Ho-Sung Song | 2017-11-21 |
| 7692985 | Semiconductor memory device capable of detecting bridge defects and bridge defect detecting method performed in the semiconductor memory device | Soon-Hong Ahn | 2010-04-06 |
| 7688651 | Methods and devices for regulating the timing of control signals in integrated circuit memory devices | Tai-young Ko | 2010-03-30 |
| 7525858 | Semiconductor memory device having local sense amplifier | Chan Yong Lee | 2009-04-28 |
| 7495472 | Circuits/methods for electrically isolating fuses in integrated circuits | Je-Min Yu | 2009-02-24 |
| 7355901 | Synchronous output buffer, synchronous memory device and method of testing access time | Min Soo Kim | 2008-04-08 |
| 7352636 | Circuit and method for generating boosted voltage in semiconductor memory device | Soo-Bong Chang | 2008-04-01 |
| 7352646 | Semiconductor memory device and method of arranging a decoupling capacitor thereof | Hyung Choi | 2008-04-01 |
| 7336518 | Layout for equalizer and data line sense amplifier employed in a high speed memory device | Soo-Bong Chang | 2008-02-26 |
| 7317645 | Redundancy repair circuit and a redundancy repair method therefor | Jun-Hyung Kim, Sung-Min Seo | 2008-01-08 |
| 7298199 | Substrate bias voltage generating circuit for use in a semiconductor memory device | Han-Gyun Jung | 2007-11-20 |
| 7184347 | Semiconductor memory devices having separate read and write global data lines | Jae-Young Lee, Sung-Min Seo | 2007-02-27 |
| 7161823 | Semiconductor memory device and method of arranging signal and power lines thereof | Jae-Young Lee, Joon Hyuk Kwon, Sung Hoon Kim, Youn-Sik Park | 2007-01-09 |
| 7110316 | Shared decoupling capacitance | Hyung Choi, Byung-Hoon Jeong | 2006-09-19 |
| 7084684 | Delay stage insensitive to operating voltage and delay circuit including the same | Doo Young Kim | 2006-08-01 |
| 7075849 | Semiconductor memory device and layout method thereof | Soo-Bong Chang, Jung-Hwa Lee, Byong-Mo Moon | 2006-07-11 |
| 7068083 | Synchronous output buffer, synchronous memory device and method of testing access time | Min Soo Kim | 2006-06-27 |
| 7057446 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level | Jong-Hyun Choi, Jae Hoon Kim, Jun-Hyung Kim, Han-Gu Sohn | 2006-06-06 |
| 7038972 | Double data rate synchronous dynamic random access memory semiconductor device | Sung-Min Seo, Kyu-hyoun Kim | 2006-05-02 |
| 6898139 | Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation | Jae Woong Lee, Sang-Seok Kang | 2005-05-24 |
| 6795372 | Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages | Myeong-O Kim, Sung-Min Seo | 2004-09-21 |
| 6777987 | Signal buffer for high-speed signal transmission and signal line driving circuit including the same | Moo Sung Chae, Sung-Min Seo | 2004-08-17 |
| 6526473 | Memory module system for controlling data input and output by connecting selected memory modules to a data line | — | 2003-02-25 |
| 6525988 | Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same | Dong-Ryul Ryu | 2003-02-25 |
| 6324119 | Data input circuit of semiconductor memory device | — | 2001-11-27 |