| 11152056 |
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Seung Yeong Seo |
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| 11145354 |
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Michael V. Ho |
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2021-03-16 |
| 10795603 |
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| 10606512 |
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| 10497424 |
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| 10483970 |
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| 10470475 |
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Kallol Mazumder |
2019-11-12 |
| 10402116 |
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| 10157648 |
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| 10148269 |
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Kallol Mazumder |
2018-12-04 |
| 9412442 |
Methods for forming a nanowire and apparatus thereof |
Eric Pop, Feng Xiong |
2016-08-09 |
| 7035152 |
System and method for redundancy memory decoding |
Jeff Koelling |
2006-04-25 |
| 6908771 |
Method for fabricating dc SQUID using high-Tc superconducting intrinsic Josephson junctions |
Hu-Jong Lee, Young Wook Son, Jong Hoon Bae |
2005-06-21 |
| 5853692 |
Process for manufacturing high purity nickel chloride by recycling waste nickel anode |
Jae-Young Lee, Jin-Gun Sohn, Seon Hwan Ahn |
1998-12-29 |
| 5805605 |
Semiconductor integrated device |
Cheol-Ha Lee |
1998-09-08 |
| 5535152 |
Semiconductor chip having a low-noise power supply arrangement |
Yong Han |
1996-07-09 |
| 5491435 |
Data sensing circuit with additional capacitors for eliminating parasitic capacitance difference between sensing control nodes of sense amplifier |
Zin-Suk Mun |
1996-02-13 |
| 5467039 |
Chip initialization signal generating circuit |
— |
1995-11-14 |
| 5045720 |
Method for selecting a spare column and a circuit thereof |
— |
1991-09-03 |
| 4929852 |
TTL to CMOS input buffer circuit |
— |
1990-05-29 |
