Issued Patents All Time
Showing 1–25 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321288 | Asymmetric read-write sequence for interconnected dies | Hyun Yoo Lee, Kang-Yong Kim, Jason McBride Brown, Vijayakrishna J. Vankayala | 2025-06-03 |
| 11669733 | Processing unit and method for computing a convolution using a hardware-implemented spiral algorithm | Deepak I. Hanagandi, Aravindan J. Busi | 2023-06-06 |
| 11580059 | Multi-port memory architecture for a systolic array | Aravindan J. Busi, Deepak I. Hanagandi, Igor Arsovski | 2023-02-14 |
| 11545198 | Multi-sense amplifier based access to a single port of a memory cell | Arjun Sankar, Sreejith Chidambaran, Igor Arsovski | 2023-01-03 |
| 11302415 | Row address comparator for a row redundancy control circuit in a memory | Sreejith Chidambaran, Prasad Vernekar | 2022-04-12 |
| 11024347 | Multiple sense amplifier and data path-based pseudo dual port SRAM | Arjun Sankar, Sreejith Chidambaran, Igor Arsovski | 2021-06-01 |
| 10964357 | Skewed sense amplifier for single-ended sensing | Anoop Delampady, Puneet Suri | 2021-03-30 |
| 10600474 | Write assist | Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose | 2020-03-24 |
| 10522217 | Column-dependent positive voltage boost for memory cell supply voltage | Eswararao Potladhurthi, George M. Braceras | 2019-12-31 |
| 10510384 | Intracycle bitline restore in high performance memory | George M. Braceras | 2019-12-17 |
| 10395700 | Integrated level translator | Sreenivasa Chaitanya Kumar Vavilla | 2019-08-27 |
| 10381069 | Write assist | Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose | 2019-08-13 |
| 10217507 | Bending circuit for static random access memory (SRAM) self-timer | Sreejith Chidambaran, Igor Arsovski | 2019-02-26 |
| 10199095 | Bit line strapping scheme for high density SRAM | Dhani Reddy Sreenivasula Reddy, Vinay Bhat Soori | 2019-02-05 |
| 10186312 | Hybrid stack write driver | Arjun Sankar | 2019-01-22 |
| 10176857 | Read and write scheme for high density SRAM | Sathisha Nanjundegowda | 2019-01-08 |
| 10170164 | Sense amplifier latch circuit and sense amplifier multiplexed latch circuit | — | 2019-01-01 |
| 10020809 | Integrated level translator and latch for fence architecture | — | 2018-07-10 |
| 9929064 | Through-substrate via (TSV) testing | Jason M. Brown | 2018-03-27 |
| 9905279 | Systems, circuits, and methods for charge sharing | — | 2018-02-27 |
| 9881669 | Wordline driver with integrated voltage level shift function | Vinay Bhatsoori | 2018-01-30 |
| 9859873 | Minimization of bias temperature instability (BTI) degradation in circuits | Navin Agarwal, Igor Arsovski, Krishnan S. Rengarajan | 2018-01-02 |
| 9787292 | High performance multiplexed latches | — | 2017-10-10 |
| 9761285 | Sense amplifier and latching scheme | Ramesh Raghavan | 2017-09-12 |
| 9721628 | Address based memory data path programming scheme | George M. Braceras | 2017-08-01 |