Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840892 | Fully digital, static, true single-phase clock (TSPC) flip-flop | Alok Chandra, Chethan Ramanna | 2020-11-17 |
| 10783956 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2020-09-22 |
| 10783958 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2020-09-22 |
| 10721104 | Feed forward equalizer with power-optimized distributed arithmetic architecture and method | Vaibhav A. Ruparelia | 2020-07-21 |
| 10659017 | Low-power scan flip-flop | Alok Chandra, Chethan Ramanna | 2020-05-19 |
| 10489455 | Scoped search engine | Samuel S. Adams, Igor Arsovski, Suparna Bhattacharya, John M. Cohn, Gary Paul Noble | 2019-11-26 |
| 10447510 | On-demand feed forward equalizer with distributed arithmetic architecture and method | Vaibhav A. Ruparelia, Panduga Shiva Shankar Reddy | 2019-10-15 |
| 10432436 | Feed forward equalizer with power-optimized distributed arithmetic architecture and method | Vaibhav A. Ruparelia | 2019-10-01 |
| 10319431 | Tunable negative bit line write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2019-06-11 |
| 10217510 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2019-02-26 |
| 9984742 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2018-05-29 |
| 9859873 | Minimization of bias temperature instability (BTI) degradation in circuits | Navin Agarwal, Igor Arsovski, Venkatraghavan Bringivijayaraghavan | 2018-01-02 |
| 9847119 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2017-12-19 |
| 9589658 | Disturb free bitcell and array | Navin Agarwal, Aditya S. Auyisetty, Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata +4 more | 2017-03-07 |
| 9570155 | Circuit to improve SRAM stability | George M. Braceras, Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreenivasula Reddy Dhani Reddy | 2017-02-14 |
| 9548104 | Boost control to improve SRAM write operation | George M. Braceras, Venkatraghavan Bringivijayaraghavan, Rahul Nayak | 2017-01-17 |
| 9496025 | Tunable negative bitline write assist and boost attenuation circuit | Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy | 2016-11-15 |
| 9460760 | Data-dependent self-biased differential sense amplifier | Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Rajesh Reddy Tummuru | 2016-10-04 |
| 9437282 | High performance sense amplifier | George M. Braceras, Venkatraghavan Bringivijayaraghavan | 2016-09-06 |
| 9324430 | Method for defining a default state of a charge trap based memory cell | Sheikh Sabiq Chishti, Toshiaki Kirihata, Deepal Wehella-Gamage | 2016-04-26 |
| 9286969 | Low power sense amplifier for static random access memory | Pankaj Agarwal, Shiju K. Kandiyil | 2016-03-15 |
| 9281045 | Refresh hidden eDRAM memory | Darren L. Anand, Venkatraghavan Bringivijayaraghavan | 2016-03-08 |
| 9251890 | Bias temperature instability state detection and correction | Navin Agarwal, Igor Arsovski, Venkatraghavan Bringivijayaraghavan | 2016-02-02 |
| 9236116 | Memory cells with read access schemes | George M. Braceras, Venkatraghavan Bringivijayaraghavan, Binu Jose | 2016-01-12 |
| 9047980 | Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines | Pankaj Agarwal, Shiju K. Kandiyil | 2015-06-02 |