Issued Patents All Time
Showing 25 most recent of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11580059 | Multi-port memory architecture for a systolic array | Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi, Deepak I. Hanagandi | 2023-02-14 |
| 11545198 | Multi-sense amplifier based access to a single port of a memory cell | Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran | 2023-01-03 |
| 11293980 | Customer-transparent logic redundancy for improved yield | John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin | 2022-04-05 |
| 11114155 | High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read | Akhilesh Patil, Eric D. Hunt-Schroeder | 2021-09-07 |
| 11101010 | Sensing circuits for charge trap transistors | Eric D. Hunt-Schroeder, Sebastian T. Ventrone, James A. Svarczkopf | 2021-08-24 |
| 11037873 | Hermetic barrier for semiconductor device | Nicholas A. Polomoff, Mark W. Kuemerle | 2021-06-15 |
| 11024347 | Multiple sense amplifier and data path-based pseudo dual port SRAM | Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran | 2021-06-01 |
| 11010133 | Parallel-prefix adder and method | Ranjan B. Lokappa | 2021-05-18 |
| 10991428 | Ternary content addressable memory | Suparna Bhattacharya, Arvind Kumar | 2021-04-27 |
| 10978143 | Multi-port high performance memory | George M. Braceras, Xiaoli Hu, Wei Zhao, Yuzheng Jin, Hao Pu +2 more | 2021-04-13 |
| 10955474 | Customer-transparent logic redundancy for improved yield | John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin | 2021-03-23 |
| 10950325 | Memory built-in self test error correcting code (MBIST ECC) for low voltage memories | Deepak I. Hanagandi, Michael A. Ziegerhofer, Valerie H. Chickanosky, Kalpesh R. Lodha | 2021-03-16 |
| 10839931 | Zero test time memory using background built-in self-test | Eric D. Hunt-Schroeder, Michael A. Ziegerhofer | 2020-11-17 |
| 10796750 | Sequential read mode static random access memory (SRAM) | Akhilesh Patil, Eric D. Hunt-Schroeder | 2020-10-06 |
| 10795430 | Activity-aware supply voltage and bias voltage compensation | Kushal Kamal | 2020-10-06 |
| 10748635 | Dynamic power analysis with per-memory instance activity customization | Kyle Holmes | 2020-08-18 |
| 10705797 | Parallel-prefix adder and method | Ranjan B. Lokappa | 2020-07-07 |
| 10566058 | Ternary content addressable memory | Suparna Bhattacharya, Arvind Kumar | 2020-02-18 |
| 10551436 | Customer-transparent logic redundancy for improved yield | John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin | 2020-02-04 |
| 10489455 | Scoped search engine | Samuel S. Adams, Suparna Bhattacharya, John M. Cohn, Gary Paul Noble, Krishnan S. Rengarajan | 2019-11-26 |
| 10446233 | Sense-line muxing scheme | Qing Li, Xiaoli Hu, Wei Zhao, Jieyao Liu | 2019-10-15 |
| 10438678 | Zero test time memory using background built-in self-test | Eric D. Hunt-Schroeder, Michael A. Ziegerhofer | 2019-10-08 |
| 10295592 | Pre-test power-optimized bin reassignment following selective voltage binning | Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert McMahon, Troy J. Perry +2 more | 2019-05-21 |
| 10217507 | Bending circuit for static random access memory (SRAM) self-timer | Venkatraghavan Bringivijayaraghavan, Sreejith Chidambaran | 2019-02-26 |
| 10204685 | Ternary content addressable memory | Suparna Bhattacharya, Arvind Kumar | 2019-02-12 |