Issued Patents All Time
Showing 51–75 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9218880 | Partial update in a ternary content addressable memory | Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach | 2015-12-22 |
| 9177646 | Implementing computational memory from content-addressable memory | — | 2015-11-03 |
| 9171125 | Limiting skew between different device types to meet performance requirements of an integrated circuit | Jeanne P. Bickford, Mark W. Kuemerle | 2015-10-27 |
| 9172371 | Majority dominant power scheme for repeated structures and structures thereof | Robert M. Houle | 2015-10-27 |
| 9088277 | Leakage reduction in output driver circuits | Travis R. Hebig | 2015-07-21 |
| 9082484 | Partial update in a ternary content addressable memory | Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach | 2015-07-14 |
| 9058903 | Methods and circuits for disrupting integrated circuit function | Sebastian T. Ventrone | 2015-06-16 |
| 8929116 | Two phase search content addressable memory with power-gated main-search | Michael T. Fragano, Travis R. Hebig | 2015-01-06 |
| 8848414 | Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system | Daniel Dobson, Travis R. Hebig | 2014-09-30 |
| 8839159 | Determining overall optimal yield point for a semiconductor wafer | Aurelius L. Graninger | 2014-09-16 |
| 8793365 | Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes | Anthony R. Bonaccio, Hayden C. Cranford, Jr., Alfred Degbotse, Joseph A. Iadanza, Todd E. Leonard +2 more | 2014-07-29 |
| 8654594 | Vdiff max limiter in SRAMs for improved yield and power | George M. Braceras, Harold Pilo | 2014-02-18 |
| 8582351 | Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability | George M. Braceras, Kevin W. Gorman, Robert M. Houle, Harold Pilo | 2013-11-12 |
| 8525546 | Majority dominant power scheme for repeated structures and structures thereof | Robert M. Houle | 2013-09-03 |
| 8521500 | Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models | Bruce Balch, Umberto Garofano, Nazmul Habib | 2013-08-27 |
| 8437201 | Word-line level shift circuit | Matthew W. Deming, Darryl R. Hill, Harold Pilo, Reid A. Wistort | 2013-05-07 |
| 8363453 | Static random access memory (SRAM) write assist circuit with leakage suppression and level control | Harold Pilo, Vinod Ramadurai | 2013-01-29 |
| 8302037 | Skewed double differential pair circuit for offset cancellation | Anthony R. Bonaccio, Hayden (Clay) Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone +1 more | 2012-10-30 |
| 8233302 | Content addressable memory with concurrent read and search/compare operations at the same memory cell | Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort | 2012-07-31 |
| 8233337 | SRAM delay circuit that tracks bitcell characteristics | George M. Braceras, Robert M. Houle, Harold Pilo | 2012-07-31 |
| 8228713 | SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same | John A. Fifield, Robert M. Houle, Harold Pilo | 2012-07-24 |
| 8218378 | Word-line level shift circuit | Matthew W. Deming, Darryl R. Hill, Harold Pilo, Reid A. Wistort | 2012-07-10 |
| 8214699 | Circuit structure and method for digital integrated circuit performance screening | David J. Wager, Michael A. Ziegerhofer | 2012-07-03 |
| 8130525 | Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM | — | 2012-03-06 |
| 8117567 | Structure for implementing memory array device with built in computation capability | — | 2012-02-14 |