Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12087383 | Virtualized scan chain testing in a random access memory (RAM) array | David Paul Hoff, Yeshwant Nagaraj Kolla, Babji Vallabhaneni | 2024-09-10 |
| 12056052 | Data L2 cache with split access | — | 2024-08-06 |
| 11223359 | Power efficient voltage level translator circuit | Anthony Correale, Jr. | 2022-01-11 |
| 10559352 | Bitline-driven sense amplifier clocking scheme | Harish Shankar, Manish Garg, Rajesh Kumar, Michael ThaiThanh Phan | 2020-02-11 |
| 9768779 | Voltage level shifters employing preconditioning circuits, and related systems and methods | Stephen Edward Liles, Manish Garg | 2017-09-19 |
| 9666269 | Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods | Harish Shankar, Manish Garg, Joshua Puckett | 2017-05-30 |
| 9557378 | Method and structure for multi-core chip product test and selective voltage binning disposition | Jeanne P. Bickford, Vikram Iyengar, Pascal A. Nsame | 2017-01-31 |
| 9396794 | Matchline retention for mitigating search and write conflict | Manish Garg | 2016-07-19 |
| 8873269 | Read only memory bitline load-balancing | Daniel R. Baratta, Konark Patel, Hoan Huu Nguyen | 2014-10-28 |
| 8233302 | Content addressable memory with concurrent read and search/compare operations at the same memory cell | Igor Arsovski, Michael T. Fragano, Reid A. Wistort | 2012-07-31 |
| 7924588 | Content addressable memory with concurrent two-dimensional search capability in both row and column directions | Igor Arsovski, Michael T. Fragano, Reid A. Wistort | 2011-04-12 |
| 7619923 | Apparatus for reducing leakage in global bit-line architectures | Anthony Correale, Jr. | 2009-11-17 |
| 7515449 | CAM asynchronous search-line switching | Igor Arsovski, Reid A. Wistort | 2009-04-07 |
| 6920525 | Method and apparatus of local word-line redundancy in CAM | Thomas Chadwick, Tarl S. Gordon, Michael R. Ouellette, Jeremy Rowland | 2005-07-19 |
| 6711040 | Saving content addressable memory power through conditional comparisons | Thomas Chadwick, Tari S. Gordon, Eric Jasinski, Michael R. Quellette | 2004-03-23 |
| 6597596 | Content addressable memory having cascaded sub-entry architecture | Tarl S. Gordon | 2003-07-22 |
| 6552920 | Saving content addressable memory power through conditional comparisons | Thomas Chadwick, Tarl S. Gordon, Eric Jasinski, Michael R. Ouellette | 2003-04-22 |
| 6512684 | Content addressable memory having cascaded sub-entry architecture | Tarl S. Gordon | 2003-01-28 |
| 6430072 | Embedded CAM test structure for fully testing all matchlines | Thomas Chadwick, Michael R. Ouellette, Jeremy Rowland | 2002-08-06 |