Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12100473 | Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods | Pramod Kolar, Ashish A. Bait | 2024-09-24 |
| 12057159 | Memory system with burst mode having logic gates as sense elements | Pramod Kolar, Gregory Christopher Burda | 2024-08-06 |
| 11699483 | Memory system with burst mode having logic gates as sense elements | Pramod Kolar, Gregory Christopher Burda | 2023-07-11 |
| 11587610 | Memory having flying bitlines for improved burst mode read operations | Pramod Kolar | 2023-02-21 |
| 11418175 | Reciprocal quantum logic inverter | Kirti N. Bhanushali, John R. Bordelon | 2022-08-16 |
| 10659015 | Method, apparatus, and system for a level shifting latch with embedded logic | Jared Buckner | 2020-05-19 |
| 9911472 | Write bitline driver for a dual voltage domain | Shaoping Ge, Chiaming Chai, Manish Garg | 2018-03-06 |
| 9768779 | Voltage level shifters employing preconditioning circuits, and related systems and methods | Rahul K. Nadkarni, Manish Garg | 2017-09-19 |
| 9640250 | Efficient compare operation | David Paul Hoff, Brian Joy Reed | 2017-05-02 |
| 9608637 | Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods | Chiaming Chai, Shaoping Ge, Chintan Shah | 2017-03-28 |
| 9548089 | Pipelining an asynchronous memory reusing a sense amp and an output latch | Satendra Kumar Maurya, Kunal Garg, Chiaming Chai, Chintan Shah | 2017-01-17 |
| 9442675 | Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods | Chiaming Chai, Shaoping Ge | 2016-09-13 |
| 9378789 | Voltage level shifted self-clocked write assistance | David Paul Hoff, Amey Kulkarni, Jason Philip Martzloff | 2016-06-28 |
| 9196330 | Mimicking multi-voltage domain wordline decoding logic for a memory array | Shaoping Ge, Chiaming Chai, Lam Nguyen, Jeffrey Herbert Fischer | 2015-11-24 |
| 9019752 | Static random access memory (SRAM) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems | Joshua Puckett, Jason Philip Martzloff | 2015-04-28 |
| 9007817 | Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods | Chiaming Chai, Shaoping Ge, Kunal Garg | 2015-04-14 |
| 8638153 | Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width | Shaoping Ge, Chiaming Chai, Lam Nguyen, Jeffrey Herbert Fischer | 2014-01-28 |
| 8456929 | Circuits, systems, and methods for dynamic voltage level shifting | Chiaming Chai, Lakshmikant Mamileti | 2013-06-04 |
| 7876631 | Self-tuning of signal path delay in circuit employing multiple voltage domains | Chiaming Chai | 2011-01-25 |
| 6473334 | Multi-ported SRAM cell with shared bit and word lines and separate read and write ports | Daniel W. Bailey, Stephen Felix | 2002-10-29 |