Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11223359 | Power efficient voltage level translator circuit | Rahul K. Nadkarni | 2022-01-11 |
| 10678988 | Integrated circuit (IC) design methods using engineering change order (ECO) cell architectures | Wolfgang Friedrich Bultmann, William Goodall, III | 2020-06-09 |
| 10380308 | Power distribution networks (PDNs) using hybrid grid and pillar arrangements | Philip Michael Iles | 2019-08-13 |
| 10366196 | Standard cell architecture for diffusion based on fin count | Benjamin J. Bowers, Tracey Della Rova, William Goodall, III | 2019-07-30 |
| 10282503 | Mitigating length-of-diffusion effect for logic cells and placement thereof | Benjamin J. Bowers, Tracey Della Rova | 2019-05-07 |
| 10236302 | Standard cell architecture for diffusion based on fin count | Benjamin J. Bowers, Tracey Della Rova, William Goodall, III | 2019-03-19 |
| 9978682 | Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods | William Goodall, III, Philip Michael Iles | 2018-05-22 |
| 9558308 | Compiler for closed-loop 1×N VLSI design | Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2017-01-31 |
| 8887113 | Compiler for closed-loop 1xN VLSI design | Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2014-11-11 |
| 8739086 | Compiler for closed-loop 1×N VLSI design | Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2014-05-27 |
| 8516428 | Methods, systems, and media to improve manufacturability of semiconductor devices | Benjamin J. Bowers | 2013-08-20 |
| 8298888 | Creating integrated circuit capacitance from gate array structures | Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi | 2012-10-30 |
| 8188516 | Creating integrated circuit capacitance from gate array structures | Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi | 2012-05-29 |
| 8156458 | Uniquification and parent-child constructs for 1xN VLSI design | Matthew W. Baker, Benjamin J. Bowers, Irfan Rashid, Paul M. Steinmetz | 2012-04-10 |
| 8141016 | Integrated design for manufacturing for 1×N VLSI design | Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2012-03-20 |
| 8136062 | Hierarchy reassembler for 1×N VLSI design | Paul M. Steinmetz, Benjamin J. Bowers, Irfan Rashid, Matthew W. Baker | 2012-03-13 |
| 8132134 | Closed-loop 1×N VLSI design system | Matthew W. Baker, Benjamin J. Bowers, Irfan Rashid, Paul M. Steinmetz | 2012-03-06 |
| 8122399 | Compiler for closed-loop 1×N VLSI design | Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2012-02-21 |
| 7966598 | Top level hierarchy wiring via 1×N compiler | Anthony L. Polomik, Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2011-06-21 |
| 7937568 | Adaptive execution cycle control method for enhanced instruction throughput | Kenichi Tsuchiya | 2011-05-03 |
| 7919819 | Interconnect components of a semiconductor device | — | 2011-04-05 |
| 7908571 | Systems and media to improve manufacturability of semiconductor devices | Benjamin J. Bowers | 2011-03-15 |
| 7904847 | CMOS circuit leakage current calculator | Nishith Rohatgi, Benjamin J. Bowers | 2011-03-08 |
| 7882385 | Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank | Nicole M. Arnold, Matthew W. Baker, Benjamin J. Bowers, Paul M. Steinmetz | 2011-02-01 |
| 7784012 | System and method for creating a standard cell library for use in circuit designs | — | 2010-08-24 |