Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7779237 | Adaptive execution frequency control method for enhanced instruction throughput | Kenichi Tsuchiya | 2010-08-17 |
| 7749816 | Systems and arrangements to interconnect components of a semiconductor device | — | 2010-07-06 |
| 7728362 | Creating integrated circuit capacitance from gate array structures | Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi | 2010-06-01 |
| 7672188 | System for blocking multiple memory read port activation | Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi | 2010-03-02 |
| 7619923 | Apparatus for reducing leakage in global bit-line architectures | Rahul K. Nadkarni | 2009-11-17 |
| 7501850 | Scannable limited switch dynamic logic (LSDL) circuit | Thomas Anderson Dick, Sven Meier, Robert K. Montoye | 2009-03-10 |
| 7500207 | Influence-based circuit design | Subhrajit Bhattacharya, Nathaniel D. Hieter, Veena S. Pureswaran, Ruchir Puri | 2009-03-03 |
| 7492013 | Systems and arrangements to interconnect components of a semiconductor device | — | 2009-02-17 |
| 7480883 | Multiple voltage integrated circuit and design method therefor | David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach | 2009-01-20 |
| 7475192 | Cache organization for power optimized memory access | Robert L. Goldiez | 2009-01-06 |
| 7470613 | Dual damascene multi-level metallization | Birendra Agarwala, Eric M. Coker, Hazara S. Rathore, Timothy D. Sullivan, Richard A. Wachnik | 2008-12-30 |
| 7395372 | Method and system for providing cache set selection which is power optimized | James Norris Dieffenderfer, Robert L. Goldiez, Thomas Philip Speier, William Robert Reohr | 2008-07-01 |
| 7343570 | Methods, systems, and media to improve manufacturability of semiconductor devices | Benjamin J. Bowers | 2008-03-11 |
| 7340712 | System and method for creating a standard cell library for reduced leakage and improved performance | — | 2008-03-04 |
| 7336100 | Single supply level converter | Rajiv V. Joshi, David S. Kung, Zhigang Pan, Ruchir Puri | 2008-02-26 |
| 7290226 | Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic | Lewis W. Dewey, III, Jason D. Hibbeler | 2007-10-30 |
| 7231621 | Speed verification of an embedded processor in a programmable logic device | Nigel G. Herron, Ahmad R. Ansari, Stephen M. Douglass, Leslie Mark DeBruyne | 2007-06-12 |
| 7224063 | Dual-damascene metallization interconnection | Birendra Agarwala, Eric M. Coker, Hazara S. Rathore, Timothy D. Sullivan, Richard A. Wachnik | 2007-05-29 |
| 7119578 | Single supply level converter | Rajiv V. Joshi, David S. Kung, Zhigang Pan, Ruchir Puri | 2006-10-10 |
| 7111266 | Multiple voltage integrated circuit and design method therefor | David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach | 2006-09-19 |
| 7091574 | Voltage island circuit placement | — | 2006-08-15 |
| 7089510 | Method and program product of level converter optimization | David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri | 2006-08-08 |
| 7080300 | Testing a programmable logic device with embedded fixed logic using a scan chain | Nigel G. Herron, Eric J. Thorne, Qingqi Wang, Thomas Anderson Dick | 2006-07-18 |
| 7017094 | Performance built-in self test system for a device and a method of use | Waleed K. Al-Assadi, Les M. DeBruyne, Thomas Anderson Dick, Jay Donnelly Grollimund | 2006-03-21 |
| 6900662 | Level translator circuit for power supply disablement | — | 2005-05-31 |