Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11314916 | Capacitance extraction | David J. Widiger, Steven Joseph Kurtz, Susan E. Cellier, Ronald D. Rose | 2022-04-26 |
| 11176308 | Extracting parasitic capacitance from circuit designs | David J. Widiger, Steven Joseph Kurtz, Susan E. Cellier, Ronald D. Rose | 2021-11-16 |
| 10685168 | Capacitance extraction for floating metal in integrated circuit | David J. Widiger, Ronald D. Rose, Harold E. Reindel | 2020-06-16 |
| 10360338 | Method for improving capacitance extraction performance by approximating the effect of distant shapes | Susan E. Cellier, Anthony D. Hagin, Adam P. Matheny, Ron D. Rose, David J. Widiger +1 more | 2019-07-23 |
| 10354041 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose +1 more | 2019-07-16 |
| 10169516 | Methods and computer program products for via capacitance extraction | Susan E. Cellier, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose, David J. Widiger | 2019-01-01 |
| 9886541 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose +1 more | 2018-02-06 |
| 8645899 | Method for extracting information for a circuit design | David J. Widiger, Ronald D. Rose, Sandy K. Kao, Gerald F. Plumb | 2014-02-04 |
| 8612918 | Method for extracting information for a circuit design | David J. Widiger, Ronald D. Rose, Sandy K. Kao, Gerald F. Plumb | 2013-12-17 |
| 8539428 | Method for extracting information for a circuit design | David J. Widiger, Ronald D. Rose, Sandy K. Kao, Gerald F. Plumb | 2013-09-17 |
| 8479131 | Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts | Ning Lu, Judith H. McCullen, Cole E. Zemke | 2013-07-02 |
| 8239804 | Method for calculating capacitance gradients in VLSI layouts using a shape processing engine | Ibrahim M. Elfadel, Tarek A. El-Moselhy, David J. Widiger, Patrick M. Williams | 2012-08-07 |
| 8201122 | Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes | Tarek Ali El Moselhy, Ibrahim M. Elfadel | 2012-06-12 |
| 8136069 | Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction | Ibrahim M. Elfadel, David J. Widiger | 2012-03-13 |
| 7290226 | Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic | Anthony Correale, Jr., Jason D. Hibbeler | 2007-10-30 |
| 7075532 | Robust tetrahedralization and triangulation method with applications in VLSI layout design and manufacturability | Maharaj Mukherjee | 2006-07-11 |
| 6854099 | Balanced accuracy for extraction | Peter A. Habitz, Thomas G. Mitchell | 2005-02-08 |