| 11314916 |
Capacitance extraction |
Steven Joseph Kurtz, Lewis W. Dewey, III, Susan E. Cellier, Ronald D. Rose |
2022-04-26 |
$5,083,000 |
| 11176308 |
Extracting parasitic capacitance from circuit designs |
Steven Joseph Kurtz, Susan E. Cellier, Lewis W. Dewey, III, Ronald D. Rose |
2021-11-16 |
$1,912,000 |
| 10929581 |
Selectively grounding fill wires |
Steven Joseph Kurtz, Ronald D. Rose |
2021-02-23 |
$3,028,000 |
| 10685168 |
Capacitance extraction for floating metal in integrated circuit |
Ronald D. Rose, Lewis W. Dewey, III, Harold E. Reindel |
2020-06-16 |
$3,682,000 |
| 10360338 |
Method for improving capacitance extraction performance by approximating the effect of distant shapes |
Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny, Ron D. Rose +1 more |
2019-07-23 |
$2,519,000 |
| 10354041 |
Process for improving capacitance extraction performance |
Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny +1 more |
2019-07-16 |
$4,107,000 |
| 10169516 |
Methods and computer program products for via capacitance extraction |
Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose |
2019-01-01 |
|
| 9886541 |
Process for improving capacitance extraction performance |
Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny +1 more |
2018-02-06 |
$2,625,000 |
| 9317644 |
Generating capacitance look-up tables for wiring patterns in the presence of metal fills |
Ibrahim M. Elfadel, Tarek Ali El Moselhy |
2016-04-19 |
$757,000 |
| 8645899 |
Method for extracting information for a circuit design |
Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb |
2014-02-04 |
$4,435,000 |
| 8612918 |
Method for extracting information for a circuit design |
Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb |
2013-12-17 |
$6,242,000 |
| 8539428 |
Method for extracting information for a circuit design |
Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb |
2013-09-17 |
$4,204,000 |
| 8495540 |
Generating capacitance look-up tables for wiring patterns in the presence of metal fills |
Ibrahim M. Elfadel, Tarek Ali El Moselhy |
2013-07-23 |
$2,085,000 |
| 8245169 |
Generating capacitance look-up tables for wiring patterns in the presence of metal fills |
Ibrahim M. Elfadel, Tarek Ali El Moselhy |
2012-08-14 |
$4,482,000 |
| 8239804 |
Method for calculating capacitance gradients in VLSI layouts using a shape processing engine |
Ibrahim M. Elfadel, Lewis W. Dewey, III, Tarek A. El-Moselhy, Patrick M. Williams |
2012-08-07 |
$7,112,000 |
| 8136069 |
Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction |
Lewis W. Dewey, III, Ibrahim M. Elfadel |
2012-03-13 |
$7,610,000 |
| 7844435 |
Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques |
Michael Alexander Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin +1 more |
2010-11-30 |
$3,507,000 |
| 7685549 |
Method of constrained aggressor set selection for crosstalk induced noise |
Debjit Sinha, Soroush Abbaspour, Ayesha Akhter, Gregory M. Schaeffer |
2010-03-23 |
$4,775,000 |
| 7475372 |
Methods for computing Miller-factor using coupled peak noise |
Chandramouli V. Kashyap, Gregory M. Schaeffer |
2009-01-06 |
$2,860,000 |
| 7346867 |
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip |
Haihua Su, Ying Liu, Byron L. Krauter, Chandramouli V. Kashyap |
2008-03-18 |
$8,037,000 |
| 7319946 |
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques |
Michael Alexander Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin +1 more |
2008-01-15 |
$35,330,000 |
| 6601222 |
Coupled noise estimation and avoidance of noise-failure using global routing information |
Sharad Mehrotra, Parsotam T. Patel |
2003-07-29 |
$10,466,000 |
| 6523149 |
Method and system to improve noise analysis performance of electrical circuits |
Sharad Mehrotra, Mark W. Wenning |
2003-02-18 |
$14,090,000 |
| 6510540 |
Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips |
Byron L. Krauter, Sharad Mehrotra, Jonathan Humphrey Saxman, Paul G. Villarrubia |
2003-01-21 |
$15,954,000 |
| 6131182 |
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros |
Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +5 more |
2000-10-10 |
$63,451,000 |
