Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6131182 | Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros | Michael P. Beakes, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce M. Fleischer +5 more | 2000-10-10 |
| 6005416 | Compiled self-resetting CMOS logic array macros | Michael P. Beakes, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce M. Fleischer +2 more | 1999-12-21 |
| 5633820 | Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability | Michael P. Beakes, Terry I. Chappell, Bruce M. Fleischer, Thao N. Nguyen | 1997-05-27 |
| 4845669 | Transporsable memory architecture | Yeong-Chang Lien, Jeffrey Tang | 1989-07-04 |