Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8201120 | Timing point selection for a static timing analysis in the presence of interconnect electrical elements | Jeffrey P. Soreff, Jeffrey G. Hemmett, Ravichander Ledalla, Vasant Rao, Fred Yang | 2012-06-12 |
| 8122404 | Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits | Debjit Sinha, Adil Bhanji, Kerim Kalafala, Natesan Venkateswaran, Chandramouli Visweswariah | 2012-02-21 |
| 7552040 | Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects | Thomas E. Rosser, Jeffrey P. Soreff | 2009-06-23 |
| 7194394 | Method and apparatus for detecting and correcting inaccuracies in curve-fitted models | Thomas E. Rosser | 2007-03-20 |
| 6131182 | Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Bruce M. Fleischer +5 more | 2000-10-10 |
| 6005416 | Compiled self-resetting CMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Bruce M. Fleischer +2 more | 1999-12-21 |
| 5454000 | Method and system for authenticating files | — | 1995-09-26 |