| 10970455 |
Apportionment aware hierarchical timing optimization |
Debjit Sinha, Nathaniel D. Hieter |
2021-04-06 |
| 10831954 |
Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs |
Debjit Sinha, Ravi Chander LEDALLA, Chaobo Li, Gregory M. Schaeffer, Michael H. Wood |
2020-11-10 |
| 10318683 |
Clock domain-independent abstracts |
Naiju K. Abdul, Jack DiLullo, Kerim Kalafala, Jeremy J. Leitzen, Manish Verma |
2019-06-11 |
| 10169503 |
Callback based constraint processing for clock domain independence |
Naiju K. Abdul, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma |
2019-01-01 |
| 9977850 |
Callback based constraint processing for clock domain independence |
Naiju K. Abdul, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma |
2018-05-22 |
| 9607124 |
Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints |
Kerim Kalafala, Ravichander Ledalla, Debjit Sinha, Chandramouli Visweswariah, Michael H. Wood |
2017-03-28 |
| 8185371 |
Modeling full and half cycle clock variability |
Sean Michael Carey, Jack DiLullo, Prashant D Joshi, Don Richard Rozales, Vern A. Victoria +1 more |
2012-05-22 |
| 8122404 |
Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits |
Debjit Sinha, Barry Lee Dorfman, Kerim Kalafala, Natesan Venkateswaran, Chandramouli Visweswariah |
2012-02-21 |
| 8103997 |
Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits |
Debjit Sinha, Soroush Abbaspour, Jeffrey M. Ritzinger |
2012-01-24 |
| 7788617 |
Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis |
Soroush Abbaspour, Peter Feldmann, Debjit Sinha |
2010-08-31 |
