Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10902167 | Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits | Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander J. Suess, Gregory M. Schaeffer | 2021-01-26 |
| 10354046 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma +3 more | 2019-07-16 |
| 10169503 | Callback based constraint processing for clock domain independence | Naiju K. Abdul, Adil Bhanji, Kerim Kalafala, Alex Rubin, Manish Verma | 2019-01-01 |
| 10169527 | Accurate statistical timing for boundary gates of hierarchical timing models | Debjit Sinha, Chandramouli Visweswariah | 2019-01-01 |
| 9985843 | Efficient parallel processing of a network with conflict constraints between nodes | David J. Hathaway, Kerim Kalafala, Ronald D. Rose | 2018-05-29 |
| 9977850 | Callback based constraint processing for clock domain independence | Naiju K. Abdul, Adil Bhanji, Kerim Kalafala, Alex Rubin, Manish Verma | 2018-05-22 |
| 9940431 | Accurate statistical timing for boundary gates of hierarchical timing models | Debjit Sinha, Chandramouli Visweswariah | 2018-04-10 |
| 9910954 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma +3 more | 2018-03-06 |
| 9853866 | Efficient parallel processing of a network with conflict constraints between nodes | David J. Hathaway, Kerim Kalafala, Ronald D. Rose | 2017-12-26 |
| 9659121 | Deterministic and statistical timing modeling for differential circuits | Jin Hu, Chad Andrew Marquart, Vasant Rao, Debjit Sinha | 2017-05-23 |
| 9608868 | Efficient parallel processing of a network with conflict constraints between nodes | David J. Hathaway, Kerim Kalafala, Ronald D. Rose | 2017-03-28 |
| 9495218 | Efficient parallel processing of a network with conflict constraints between nodes | David J. Hathaway, Kerim Kalafala, Ronald D. Rose | 2016-11-15 |
| 8776004 | Method for improving static timing analysis and optimizing circuits using reverse merge | Frank Borkam, David J. Hathaway, Kerim Kalafala, Vasant Rao, Alex Rubin | 2014-07-08 |
| 8549452 | Method for supporting multiple libraries characterized at different process, voltage and temperature points | Revanta Banerji, Soroush Abbaspour, Peter Feldmann | 2013-10-01 |
| 8056038 | Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip | Kerim Kalafala, David J. Hathaway, Jeffrey G. Hemmett | 2011-11-08 |