Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11314916 | Capacitance extraction | David J. Widiger, Steven Joseph Kurtz, Lewis W. Dewey, III, Susan E. Cellier | 2022-04-26 |
| 11176308 | Extracting parasitic capacitance from circuit designs | David J. Widiger, Steven Joseph Kurtz, Susan E. Cellier, Lewis W. Dewey, III | 2021-11-16 |
| 11120193 | Analysis of coupled noise for integrated circuit design | Steven Joseph Kurtz, Mark A. Lavin, Richard W. Taggart, Vladimir Zolotov | 2021-09-14 |
| 10929581 | Selectively grounding fill wires | Steven Joseph Kurtz, David J. Widiger | 2021-02-23 |
| 10685168 | Capacitance extraction for floating metal in integrated circuit | David J. Widiger, Lewis W. Dewey, III, Harold E. Reindel | 2020-06-16 |
| 10394999 | Analysis of coupled noise for integrated circuit design | Steven Joseph Kurtz, Mark A. Lavin, Richard W. Taggart, Vladimir Zolotov | 2019-08-27 |
| 10354041 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny +1 more | 2019-07-16 |
| 10169516 | Methods and computer program products for via capacitance extraction | Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny, David J. Widiger | 2019-01-01 |
| 9985843 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Kerim Kalafala | 2018-05-29 |
| 9886541 | Process for improving capacitance extraction performance | Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny +1 more | 2018-02-06 |
| 9853866 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Kerim Kalafala | 2017-12-26 |
| 9836571 | Applying random nets credit in an efficient static timing analysis | David J. Hathaway | 2017-12-05 |
| 9646125 | Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor | John A. Fifield, Mark C. Hakey, Jason D. Hibbeler, James S. Nakos, Tak H. Ning +3 more | 2017-05-09 |
| 9608868 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Kerim Kalafala | 2017-03-28 |
| 9495218 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Kerim Kalafala | 2016-11-15 |
| 9418190 | Virtual sub-net based routing | Gi-Joon Nam, Sven Peyer, Sourav Saha | 2016-08-16 |
| 9245084 | Virtual sub-net based routing | Gi-Joon Nam, Sven Peyer, Sourav Saha | 2016-01-26 |
| 8655634 | Modeling loading effects of a transistor network | David J. Hathaway, Vasant Rao, Ali Sadigh, Jeffrey P. Soreff, David W. Winston | 2014-02-18 |
| 8645899 | Method for extracting information for a circuit design | David J. Widiger, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb | 2014-02-04 |
| 8640062 | Rapid estimation of temperature rise in wires due to Joule heating | Kanak B. Agarwal, Sani R. Nassif, Chenggang Xu | 2014-01-28 |
| 8612918 | Method for extracting information for a circuit design | David J. Widiger, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb | 2013-12-17 |
| 8539428 | Method for extracting information for a circuit design | David J. Widiger, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb | 2013-09-17 |
| 7913216 | Accurate parasitics estimation for hierarchical customized VLSI design | Yiu-Hing Chan, Jun Zhou | 2011-03-22 |
| 7127689 | Method for preventing circuit failures due to gate oxide leakage | Paul D. Kartschoke, Thomas G. Mitchell, Norman J. Rohrer | 2006-10-24 |
| 7089513 | Integrated circuit design for signal integrity, avoiding well proximity effects | Karen Bard, Michael Sitko | 2006-08-08 |